Kb NV Memory, Iicsclsfp | Xilinx SP605 instruction

Chapter 1: SP605 Evaluation Board

Table 1-19:IIC Bus Connections

	U1 FPGA Pin	Schematic	Connected To	Level-Shifted	Level-Shifted
	U1 FPGA Pin	Netname	Connected To	Connection	Net Name
		Netname		Connection	Net Name

	R22	IIC_SDA_MAIN	J2.C31, U4.5(1)	–	–
	T21	IIC_SCL_MAIN	J2.C30, U4.6(1)	–	–
	AA4	IIC_SDA_DVI	Q8.2, U31.14	Q8.3, P3.7	IIC_SDA_DVI_F

	W13	IIC_SCL_DVI	Q7.2, U31.15	Q7.3, P3.6	IIC_CLK_DVI_F

	E6	IIC_SDA_SFP	P2.4	–	–

	E5	IIC_SCL_SFP	P2.5	–	–

Notes:

1.U4 IIC bus signals are resistively coupled with 0 ohm resistors

2.Legend

J2, FMC LPC Connector P2, SFP Module Connector P3, DVI Connector

Qn.n, Level-Shifting Transistor U31, Chrontel CH7301C

8-Kb NV Memory

The SP605 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U4). The IIC address of U4 is 0b1010100, and U4 is not write protected (WP pin 7 is tied to GND).

The IIC memory is shown in Figure 1-12.

VCC3V3

1

R6

1

R5

1

R50

IIC Address 0b1010100

									1.0K		1.0K		DNP
									5%		5%		1%
								2	1/10W	2	1/10W	2	1/16W				VCC3V3
															U4		VCC3V3
															U4
IIC_SCL_MAIN					1			2					6	SCL
IIC_SCL_MAIN	1			2									6	SCL		7
IIC_SDA_MAIN	1			2									5	SDA	WP	7	1
IIC_SDA_MAIN			5%		R291	0	5%	1/16W						SDA	WP			C40
	R292	0		1/16W
													1
													1	A0			0.1UF
													2	A0		8	2	X5R
													2	A1	VCC	8	2	X5R
2	J45												3	A2	GND	4		10V
2	1
	H-1X2											1	M24C08-WDW6TP
	H-1X2											1	R216
													R216
External Access													0
External Access												2	5%
Header												2
Header
																	UG526_12 _100509

Figure 1-12: IIC Memory U4

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SP605 Hardware User Guide

UG526 (v1.1.1) February 1, 2010

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Xilinx SP605 manual Kb NV Memory, Iicsclsfp

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optional Revision History Date Version Revision Table of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide SP605 Evaluation Board Additional Information Features SP605 Evaluation Board Block Diagram Overview SP605 Features Feature Detailed Description SP605 Features Cont’d Configuration SP605 Evaluation Board SP605 Features Cont’dSpartan-6 XC6SLX45T-3FGG484 Fpga MB DDR3 Component Memory Voltage RailsDetailed Description 2I/O Voltage Rail of Fpga Banks Schematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory Connections U1 Fpga SPI x4 Flash 3J17 SPI Flash Programming Header Schematic Net Name Detailed Description 6SPI x4 Memory Connections Linear BPI Flash Pin Number Pin Name FLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144I USB Jtag Clock Generation Oscillator Differential Oscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential Multi-Gigabit Transceivers GTP MGTs MGT Refclk Smarefclkn 11PCIe Edge Connector Connections U1 Fpga Pin P4 PCIe Edge ConnectorPCI Express Endpoint Connectivity References SFP Module Connector Sfpclkqop 14PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga Pin PHYRXD7 USB-to-UART Bridge 17 USB-to-UART Connections DVI Codec IIC Bus 11IIC Bus Topology Kb NV Memory Iicsclsfp Iicsdamain SDA Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 13Ethernet PHY Status LEDs Fpga Init and Done LEDs 22 Fpga Init and Done LED Connections User I/O User LEDs23User LED Connections U1 Fpga Pin Controlled LED User Pushbutton Switches SW6 User DIP Switch User SIP Header U1 Fpga Pin User SMA Gpio Usersmagpion Usersmagpiop Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1 Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and 12V Input Power Jack/Switch Onboard Power Regulation Power Management UCD9240PFC Configuration Options 30SP605 Fpga Configuration Modes M10 Bus WidthConfiguration Solution User Guide Section SP605 Evaluation Board Table A-1Default Switch Settings Function/Type Default FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET Fmcpwrgoodflashrstb NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References