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Xilinx SP605 Kb NV Memory, 19 IIC Bus Connections, Schematic, Connected To, Level-Shifted, Header

Models: SP605

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Table 1-19:IIC Bus Connections

Chapter 1: SP605 Evaluation Board

Table 1-19:IIC Bus Connections

	U1 FPGA Pin	Schematic	Connected To	Level-Shifted	Level-Shifted
	U1 FPGA Pin	Netname	Connected To	Connection	Net Name
		Netname		Connection	Net Name

	R22	IIC_SDA_MAIN	J2.C31, U4.5(1)	–	–
	T21	IIC_SCL_MAIN	J2.C30, U4.6(1)	–	–
	AA4	IIC_SDA_DVI	Q8.2, U31.14	Q8.3, P3.7	IIC_SDA_DVI_F

	W13	IIC_SCL_DVI	Q7.2, U31.15	Q7.3, P3.6	IIC_CLK_DVI_F

	E6	IIC_SDA_SFP	P2.4	–	–

	E5	IIC_SCL_SFP	P2.5	–	–

Notes:

1.U4 IIC bus signals are resistively coupled with 0 ohm resistors

2.Legend

J2, FMC LPC Connector P2, SFP Module Connector P3, DVI Connector

Qn.n, Level-Shifting Transistor U31, Chrontel CH7301C

8-Kb NV Memory

The SP605 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U4). The IIC address of U4 is 0b1010100, and U4 is not write protected (WP pin 7 is tied to GND).

The IIC memory is shown in Figure 1-12.

VCC3V3

1

R6

1

R5

1

R50

IIC Address 0b1010100

									1.0K		1.0K		DNP
									5%		5%		1%
								2	1/10W	2	1/10W	2	1/16W				VCC3V3
															U4		VCC3V3
															U4
IIC_SCL_MAIN					1			2					6	SCL
IIC_SCL_MAIN	1			2									6	SCL		7
IIC_SDA_MAIN	1			2									5	SDA	WP	7	1
IIC_SDA_MAIN			5%		R291	0	5%	1/16W						SDA	WP			C40
	R292	0		1/16W
													1
													1	A0			0.1UF
													2	A0		8	2	X5R
													2	A1	VCC	8	2	X5R
2	J45												3	A2	GND	4		10V
2	1
	H-1X2											1	M24C08-WDW6TP
	H-1X2											1	R216
													R216
External Access													0
External Access												2	5%
Header												2
Header
																	UG526_12 _100509

Figure 1-12: IIC Memory U4

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SP605 Hardware User Guide

UG526 (v1.1.1) February 1, 2010

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Xilinx SP605 Kb NV Memory, 19 IIC Bus Connections, Schematic, Connected To, Level-Shifted, IIC Address 0b1010100, Header

Contents

UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideGuide Subtitle optional Updated Figure 1-17 and Figure Revision HistoryDate VersionTable of Contents Preface About This GuideChapter 1 SP605 Evaluation Board Appendix A Default Jumper and Switch Settings Appendix B VITA 57.1 FMC LPC Connector PinoutAppendix C SP605 Master UCF Appendix D References Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC ConnectorGuide Contents Appendix A, “Default Jumper and Switch Settings.”Appendix B, “VITA 57.1 FMC LPC Connector Pinout.” About This GuideAdditional Support Resources Preface About This GuideSP605 Evaluation Board ChapterOverview Additional InformationFeatures 5. System ACE CF and CompactFlash Connector 6. USB JTAG10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY Chapter 1 SP605 Evaluation BoardBlock Diagram 17. Switches18. VITA 57.1 FMC LPC Connector Configuration Options 4. Linear BPI Flash 5. System ACE CF and CompactFlash ConnectorSP605 Features FeatureRelated Xilinx Documents Detailed DescriptionSP605 Features Cont’d Detailed DescriptionFeature Linear BPI FlashConfiguration 1. Spartan-6 XC6SLX45T-3FGG484 FPGAReferences SP605 Features Cont’dSignal Name 2. 128 MB DDR3 Component MemoryI/O Voltage Rails Table 1-2 I/O Voltage Rail of FPGA BanksSchematic Net Name Table 1-4 FPGA On-Chip OCT Termination External Resistor RequirementsU1 FPGA Pin FPGA Pin NumberDDR3 Component Memory Connections Cont’d ReferencesDetailed Description Memory U423. SPI x4 Flash SilkscreenFigure 1-3 J17 SPI Flash Programming Header Figure 1-4 SPI Flash Interface TopologyDetailed Description Table 1-6 SPI x4 Memory Connections SPI MEM U32SPI HDR J17 Schematic Net Name4. Linear BPI Flash Figure 1-5 Linear BPI Flash InterfaceTable 1-7 Linear Flash Connections U25 BPI FLASHDetailed Description Table 1-7 Linear Flash Connections Cont’d Schematic Net NameU1 FPGA Pin U25 BPI FLASH5. System ACE CF and CompactFlash Connector FPGA Design Considerations for the Configuration FlashReferences Chapter 1 SP605 Evaluation BoardSchematic Net Name1 Table 1-8 System ACE CF ConnectionsU17 XCCACETQ144I Detailed DescriptionFigure 1-6 JTAG Chain Diagram 6. USB JTAGTable 1-8 System ACE CF Connections Cont’d Schematic Net Name7. Clock Generation Oscillator DifferentialFigure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19 ReferencesOscillator Socket Single-Ended, 2.5V or Figure 1-8 SP605 X2 Oscillator Socket Pin 1 Location IdentifiersFigure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers Silkscreened outline has beveled corner Socket has notch in crossbarSMA Connectors Differential 8. Multi-Gigabit Transceivers GTP MGTsTable 1-9 SP605 Clock Source Connections SourceFigure 1-10 GTP SMA Clock SMA MGT ConnectorsMGT REFCLK Chapter 1 SP605 Evaluation BoardDetailed Description Table 1-10 GTP SMA Clock Connections SMA PinSchematic Net Name U1 FPGA PinTable 1-11 PCIe Edge Connector Connections P4 PCIe Edge Connector9. PCI Express Endpoint Connectivity Chapter 1 SP605 Evaluation BoardReferences Detailed DescriptionProduct information 10. SFP Module Connector SFP Control/Status SignalP2 SFP Module Connector Table 1-12 SFP Module Control and StatusTable 1-14 PHY Configuration Pins 11. 10/100/1000 Tri-Speed Ethernet PHYBit2 Bit1Table 1-15 Ethernet PHY Connections Cont’d ReferencesChapter 1 SP605 Evaluation Board U1 FPGA PinTable 1-16 USB Type B Pin Assignments and Signal Definitions USB Connector12. USB-to-UART Bridge DescriptionSchematic Net 13. DVI CODECTable 1-18 DVI Controller Connections U31 Chrontel CH7301C14. IIC Bus Figure 1-11 IIC Bus TopologyDetailed Description Schematic External Access8-Kb NV Memory Table 1-19 IIC Bus ConnectionsSchematic Netname Detailed Description Table 1-20 IIC Memory ConnectionsIIC Memory U4 References15. Status LEDs Table 1-21 Status LEDsColor LabelDirection Indicator DUP TX RX Ethernet PHY Status LEDsLink Rate Mbps 100 1000 P1FPGA INIT and DONE LEDs VCC2V5FPGAINITB FPGADONEUser LEDs User Pushbutton Switches User DIP Switch User SIP Header 16. User I/OUser LEDs User SMA GPIOUser Pushbutton Switches Figure 1-16 User Pushbutton Switch TypicalTable 1-24 Pushbutton Switch Connections Switch PinUser DIP Switch Figure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch ConnectionsDIP Switch Pin Schematic Net NameUser SIP Header Figure 1-18 User SIP Header J55Table 1-26 User SIP Header Connections Schematic Net NameUser SMA GPIO Figure 1-19 User SMA GPIOTable 1-27 User SMA Connections GPIO SMA Pin17. Switches Power On/Off Slide Switch SW2Power On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low SYSACERESETB Pushbutton SW9 Active-LowSYSACERESETB Pushbutton SW9 Active-Low Figure 1-22 System ACE CF RESETB Pushbutton SW9FPGAPROGB Pushbutton SW3 Active-Low Figure 1-21 FPGA PROGB Pushbutton SW3System ACE CF CompactFlash Image Select DIP Switch S1 Active-High Figure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1SDMX-4-X Chapter 1 SP605 Evaluation BoardMode DIP Switch SW1 Active-High Figure 1-24 FPGA Mode DIP Switch SW1R9 SDMX-2-X References18. VITA 57.1 FMC LPC Connector Chapter 1 SP605 Evaluation BoardTable 1-28 VITA 57.1 FMC LPC Connections J63 FMCLPC Pin Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”Power Management AC Adapter and 12V Input Power Jack/SwitchTable 1-28 VITA 57.1 FMC LPC Connections Cont’d Schematic Net NameOnboard Power Regulation Power ManagementPower Supply Figure 1-25 Onboard Power RegulatorsTable 1-29 Onboard Power System Devices Power Rail NetDevice Type ReferenceConfiguration Options Configuration Options“5. System ACE CF and CompactFlash Connector,” page Table 1-30 SP605 FPGA Configuration ModesChapter 1 SP605 Evaluation Board SP605 Hardware User GuideUG526 v1.1.1 February 1 Default Jumper and Switch Settings Table A-1 Default Switch SettingsDefault Appendix AAppendix A Default Jumper and Switch Settings Table A-2 Default Jumper SettingsCF Error LED JumperVITA 57.1 FMC LPC Connector Pinout Figure B-1 FMC LPC Connector PinoutAppendix B UG526 v1.1.1 February 1Appendix B VITA 57.1 FMC LPC Connector Pinout SP605 Hardware User GuideUG526 v1.1.1 February 1 SP605 Master UCF Appendix CUG526 v1.1.1 February 1 Appendix C SP605 Master UCF SP605 Hardware User GuideUG526 v1.1.1 February 1 UG526 v1.1.1 February 1 LOC = AA20Appendix C SP605 Master UCF 3. Series resistors are included Appendix C SP605 Master UCF SP605 Hardware User GuideUG526 v1.1.1 February 1 References Appendix D