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Xilinx manual SP605 Master UCF, Appendix C, UG526 v1.1.1 February 1

Models: SP605

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Appendix C

Appendix C

SP605 Master UCF

The UCF template is provided for designs that target the SP605. Net names provided in the constraints below correlate with net names on the SP605 rev. C schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL. See the Constraints Guide for more information.

NET "CLK_33MHZ_SYSACE"	LOC = "N19";	## 93	on U17
NET "CPU_RESET"	LOC = "H8";	## 2	on SW6 pushbutton (active-high)
##
NET "DVI_D0"	LOC = "K16";	## 63	on U31 (thru series R39 47.5 ohm)
NET "DVI_D1"	LOC = "U19";	## 62	on U31 (thru series R38 47.5 ohm)
NET "DVI_D2"	LOC = "T20";	## 61	on U31 (thru series R37 47.5 ohm)
NET "DVI_D3"	LOC = "N16";	## 60	on U31 (thru series R36 47.5 ohm)
NET "DVI_D4"	LOC = "P16";	## 59	on U31 (thru series R35 47.5 ohm)
NET "DVI_D5"	LOC = "M17";	## 58	on U31 (thru series R34 47.5 ohm)
NET "DVI_D6"	LOC = "M18";	## 55	on U31 (thru series R33 47.5 ohm)
NET "DVI_D7"	LOC = "R15";	## 54	on U31 (thru series R32 47.5 ohm)
NET "DVI_D8"	LOC = "R16";	## 53	on U31 (thru series R31 47.5 ohm)
NET "DVI_D9"	LOC = "P17";	## 52	on U31 (thru series R30 47.5 ohm)
NET "DVI_D10"	LOC = "P18";	## 51	on U31 (thru series R29 47.5 ohm)
NET "DVI_D11"	LOC = "R17";	## 50	on U31 (thru series R28 47.5 ohm)
NET "DVI_DE"	LOC = "J17";	## 2	on U31 (thru series R40 47.5 ohm)
NET "DVI_GPIO1"	LOC = "D22";	## 18	on U31
NET "DVI_H"	LOC = "J16";	## 4	on U31 (thru series R41 47.5 ohm)
NET "DVI_RESET_B"	LOC = "L15";	## 13	on U31
NET "DVI_V"	LOC = "B22";	## 5	on U31 (thru series R42 47.5 ohm)
NET "DVI_XCLK_N"	LOC = "C22";	## 56	on U31
NET "DVI_XCLK_P"	LOC = "C20";	## 57	on U31
##
NET "FLASH_A0"	LOC = "N22";	## 29	on U25
NET "FLASH_A1"	LOC = "N20";	## 25	on U25
NET "FLASH_A2"	LOC = "M22";	## 24	on U25
NET "FLASH_A3"	LOC = "M21";	## 23	on U25
NET "FLASH_A4"	LOC = "L19";	## 22	on U25
NET "FLASH_A5"	LOC = "K20";	## 21	on U25
NET "FLASH_A6"	LOC = "H22";	## 20	on U25
NET "FLASH_A7"	LOC = "H21";	## 19	on U25
NET "FLASH_A8"	LOC = "L17";	## 8	on U25
NET "FLASH_A9"	LOC = "K17";	## 7	on U25
NET "FLASH_A10"	LOC = "G22";	## 6	on U25
NET "FLASH_A11"	LOC = "G20";	## 5	on U25
NET "FLASH_A12"	LOC = "K18";	## 4	on U25
NET "FLASH_A13"	LOC = "K19";	## 3	on U25
NET "FLASH_A14"	LOC = "H20";	## 2	on U25
NET "FLASH_A15"	LOC = "J19";	## 1	on U25
NET "FLASH_A16"	LOC = "E22";	## 55	on U25
NET "FLASH_A17"	LOC = "E20";	## 18	on U25
NET "FLASH_A18"	LOC = "F22";	## 17	on U25
NET "FLASH_A19"	LOC = "F21";	## 16	on U25
NET "FLASH_A20"	LOC = "H19";	## 11	on U25
NET "FLASH_A21"	LOC = "H18";	## 10	on U25
NET "FLASH_A22"	LOC = "F20";	## 9	on U25
NET "FLASH_A23"	LOC = "G19";	## 26	on U25
NET "FPGA_D0_DIN_MISO_MISO1"	LOC = "AA20";	## 34	on U25, 8 on U32 (thru series R132 100 ohm), 6 on J17
NET "FPGA_D1_MISO2"	LOC = "R13";	## 36	on U25, 3 on J17
NET "FPGA_D2_MISO3"	LOC = "T14";	## 39	on U25, 2 on J17
NET "FLASH_D3"	LOC = "AA6";	## 41	on U25
NET "FLASH_D4"	LOC = "AB6";	## 47	on U25
NET "FLASH_D5"	LOC = "Y5";	## 49	on U25
NET "FLASH_D6"	LOC = "AB5";	## 51	on U25
NET "FLASH_D7"	LOC = "W9";	## 53	on U25
NET "FLASH_D8"	LOC = "T7";	## 35	on U25
NET "FLASH_D9"	LOC = "U6";	## 37	on U25
NET "FLASH_D10"	LOC = "AB19";	## 40	on U25
NET "FLASH_D11"	LOC = "AA18";	## 42	on U25
NET "FLASH_D12"	LOC = "AB18";	## 48	on U25
NET "FLASH_D13"	LOC = "Y13";	## 50	on U25
NET "FLASH_D14"	LOC = "AA12";	## 52	on U25
NET "FLASH_D15"	LOC = "AB12";	## 54	on U25
NET "FLASH_WAIT"	LOC = "T18";	## 56	on U25

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Xilinx manual SP605 Master UCF, Appendix C, UG526 v1.1.1 February 1

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalGuide Subtitle optional Revision History Updated Figure 1-17 and FigureDate VersionPreface About This Guide Table of ContentsChapter 1 SP605 Evaluation Board Appendix B VITA 57.1 FMC LPC Connector Pinout Appendix A Default Jumper and Switch SettingsAppendix C SP605 Master UCF Appendix D References Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC ConnectorAppendix A, “Default Jumper and Switch Settings.” Guide ContentsAppendix B, “VITA 57.1 FMC LPC Connector Pinout.” About This GuidePreface About This Guide Additional Support ResourcesChapter SP605 Evaluation BoardOverview Additional Information5. System ACE CF and CompactFlash Connector 6. USB JTAG Features10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY Chapter 1 SP605 Evaluation Board17. Switches Block Diagram18. VITA 57.1 FMC LPC Connector Configuration Options 4. Linear BPI Flash 5. System ACE CF and CompactFlash ConnectorFeature SP605 FeaturesRelated Xilinx Documents Detailed DescriptionDetailed Description SP605 Features Cont’dFeature Linear BPI Flash1. Spartan-6 XC6SLX45T-3FGG484 FPGA ConfigurationReferences SP605 Features Cont’d2. 128 MB DDR3 Component Memory Signal NameI/O Voltage Rails Table 1-2 I/O Voltage Rail of FPGA BanksTable 1-4 FPGA On-Chip OCT Termination External Resistor Requirements Schematic Net NameU1 FPGA Pin FPGA Pin NumberReferences DDR3 Component Memory Connections Cont’dDetailed Description Memory U42Silkscreen 3. SPI x4 FlashFigure 1-3 J17 SPI Flash Programming Header Figure 1-4 SPI Flash Interface TopologySPI MEM U32 Detailed Description Table 1-6 SPI x4 Memory ConnectionsSPI HDR J17 Schematic Net NameFigure 1-5 Linear BPI Flash Interface 4. Linear BPI FlashTable 1-7 Linear Flash Connections U25 BPI FLASHSchematic Net Name Detailed Description Table 1-7 Linear Flash Connections Cont’dU1 FPGA Pin U25 BPI FLASHFPGA Design Considerations for the Configuration Flash 5. System ACE CF and CompactFlash ConnectorReferences Chapter 1 SP605 Evaluation BoardTable 1-8 System ACE CF Connections Schematic Net Name1U17 XCCACETQ144I Detailed Description6. USB JTAG Figure 1-6 JTAG Chain DiagramTable 1-8 System ACE CF Connections Cont’d Schematic Net NameOscillator Differential 7. Clock GenerationFigure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19 ReferencesFigure 1-8 SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orFigure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers Silkscreened outline has beveled corner Socket has notch in crossbar8. Multi-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialTable 1-9 SP605 Clock Source Connections SourceSMA MGT Connectors Figure 1-10 GTP SMA ClockMGT REFCLK Chapter 1 SP605 Evaluation BoardSMA Pin Detailed Description Table 1-10 GTP SMA Clock ConnectionsSchematic Net Name U1 FPGA PinP4 PCIe Edge Connector Table 1-11 PCIe Edge Connector Connections9. PCI Express Endpoint Connectivity Chapter 1 SP605 Evaluation BoardDetailed Description ReferencesProduct information SFP Control/Status Signal 10. SFP Module ConnectorP2 SFP Module Connector Table 1-12 SFP Module Control and Status11. 10/100/1000 Tri-Speed Ethernet PHY Table 1-14 PHY Configuration PinsBit2 Bit1References Table 1-15 Ethernet PHY Connections Cont’dChapter 1 SP605 Evaluation Board U1 FPGA PinUSB Connector Table 1-16 USB Type B Pin Assignments and Signal Definitions12. USB-to-UART Bridge Description13. DVI CODEC Schematic NetTable 1-18 DVI Controller Connections U31 Chrontel CH7301CFigure 1-11 IIC Bus Topology 14. IIC BusDetailed Description External Access Schematic8-Kb NV Memory Table 1-19 IIC Bus ConnectionsDetailed Description Table 1-20 IIC Memory Connections Schematic NetnameIIC Memory U4 ReferencesTable 1-21 Status LEDs 15. Status LEDsColor LabelEthernet PHY Status LEDs Direction Indicator DUP TX RXLink Rate Mbps 100 1000 P1VCC2V5 FPGA INIT and DONE LEDsFPGAINITB FPGADONE16. User I/O User LEDs User Pushbutton Switches User DIP Switch User SIP HeaderUser LEDs User SMA GPIOFigure 1-16 User Pushbutton Switch Typical User Pushbutton SwitchesTable 1-24 Pushbutton Switch Connections Switch PinFigure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch Connections User DIP SwitchDIP Switch Pin Schematic Net NameFigure 1-18 User SIP Header J55 User SIP HeaderTable 1-26 User SIP Header Connections Schematic Net NameFigure 1-19 User SMA GPIO User SMA GPIOTable 1-27 User SMA Connections GPIO SMA PinPower On/Off Slide Switch SW2 17. SwitchesPower On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low SYSACERESETB Pushbutton SW9 Active-LowFigure 1-22 System ACE CF RESETB Pushbutton SW9 SYSACERESETB Pushbutton SW9 Active-LowFPGAPROGB Pushbutton SW3 Active-Low Figure 1-21 FPGA PROGB Pushbutton SW3Figure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 Active-HighSDMX-4-X Chapter 1 SP605 Evaluation BoardFigure 1-24 FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighR9 SDMX-2-X ReferencesChapter 1 SP605 Evaluation Board 18. VITA 57.1 FMC LPC ConnectorJ63 FMC Table 1-28 VITA 57.1 FMC LPC ConnectionsLPC Pin Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”AC Adapter and 12V Input Power Jack/Switch Power ManagementTable 1-28 VITA 57.1 FMC LPC Connections Cont’d Schematic Net NamePower Management Onboard Power RegulationPower Supply Figure 1-25 Onboard Power RegulatorsPower Rail Net Table 1-29 Onboard Power System DevicesDevice Type ReferenceConfiguration Options Configuration Options“5. System ACE CF and CompactFlash Connector,” page Table 1-30 SP605 FPGA Configuration ModesSP605 Hardware User Guide Chapter 1 SP605 Evaluation BoardUG526 v1.1.1 February 1 Table A-1 Default Switch Settings Default Jumper and Switch SettingsDefault Appendix ATable A-2 Default Jumper Settings Appendix A Default Jumper and Switch SettingsCF Error LED JumperFigure B-1 FMC LPC Connector Pinout VITA 57.1 FMC LPC Connector PinoutAppendix B UG526 v1.1.1 February 1SP605 Hardware User Guide Appendix B VITA 57.1 FMC LPC Connector PinoutUG526 v1.1.1 February 1 Appendix C SP605 Master UCFUG526 v1.1.1 February 1 SP605 Hardware User Guide Appendix C SP605 Master UCFUG526 v1.1.1 February 1 LOC = AA20 UG526 v1.1.1 February 1Appendix C SP605 Master UCF 3. Series resistors are included SP605 Hardware User Guide Appendix C SP605 Master UCFUG526 v1.1.1 February 1 Appendix D References