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manual Appendix B VITA 57.1 FMC LPC Connector Pinout, SP605 Hardware User Guide
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Block Diagram
Onboard Power Regulation Configuration Options
SYSACERESETB Pushbutton SW9 Active-Low
Default Jumper and Switch Settings
Signal Name
Direction Indicator DUP TX RX
Power Management
Updated -17 and Figure
External Access
System ACE CF and CompactFlash Connector 6. USB JTAG
Page 60
Image 60
Appendix B:
VITA 57.1 FMC LPC Connector Pinout
60
www.xilinx.com
SP605 Hardware User Guide
UG526 (v1.1.1) February 1, 2010
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Contents
UG526 v1.1.1 February 1, 2010 optional
SP605 Hardware User Guide
Guide Subtitle optional
Updated Figure 1-17 and Figure
Revision History
Date
Version
Table of Contents
Preface About This Guide
Chapter 1 SP605 Evaluation Board
Appendix A Default Jumper and Switch Settings
Appendix B VITA 57.1 FMC LPC Connector Pinout
Appendix C SP605 Master UCF Appendix D References
Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC Connector
Guide Contents
Appendix A, “Default Jumper and Switch Settings.”
Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”
About This Guide
Additional Support Resources
Preface About This Guide
SP605 Evaluation Board
Chapter
Overview
Additional Information
Features
5. System ACE CF and CompactFlash Connector 6. USB JTAG
10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY
Chapter 1 SP605 Evaluation Board
Block Diagram
17. Switches
18. VITA 57.1 FMC LPC Connector Configuration Options
4. Linear BPI Flash 5. System ACE CF and CompactFlash Connector
SP605 Features
Feature
Related Xilinx Documents
Detailed Description
SP605 Features Cont’d
Detailed Description
Feature
Linear BPI Flash
Configuration
1. Spartan-6 XC6SLX45T-3FGG484 FPGA
References
SP605 Features Cont’d
Signal Name
2. 128 MB DDR3 Component Memory
I/O Voltage Rails
Table 1-2 I/O Voltage Rail of FPGA Banks
Schematic Net Name
Table 1-4 FPGA On-Chip OCT Termination External Resistor Requirements
U1 FPGA Pin
FPGA Pin Number
DDR3 Component Memory Connections Cont’d
References
Detailed Description
Memory U42
3. SPI x4 Flash
Silkscreen
Figure 1-3 J17 SPI Flash Programming Header
Figure 1-4 SPI Flash Interface Topology
Detailed Description Table 1-6 SPI x4 Memory Connections
SPI MEM U32
SPI HDR J17
Schematic Net Name
4. Linear BPI Flash
Figure 1-5 Linear BPI Flash Interface
Table 1-7 Linear Flash Connections
U25 BPI FLASH
Detailed Description Table 1-7 Linear Flash Connections Cont’d
Schematic Net Name
U1 FPGA Pin
U25 BPI FLASH
5. System ACE CF and CompactFlash Connector
FPGA Design Considerations for the Configuration Flash
References
Chapter 1 SP605 Evaluation Board
Schematic Net Name1
Table 1-8 System ACE CF Connections
U17 XCCACETQ144I
Detailed Description
Figure 1-6 JTAG Chain Diagram
6. USB JTAG
Table 1-8 System ACE CF Connections Cont’d
Schematic Net Name
7. Clock Generation
Oscillator Differential
Figure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19
References
Oscillator Socket Single-Ended, 2.5V or
Figure 1-8 SP605 X2 Oscillator Socket Pin 1 Location Identifiers
Figure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers
Silkscreened outline has beveled corner Socket has notch in crossbar
SMA Connectors Differential
8. Multi-Gigabit Transceivers GTP MGTs
Table 1-9 SP605 Clock Source Connections
Source
Figure 1-10 GTP SMA Clock
SMA MGT Connectors
MGT REFCLK
Chapter 1 SP605 Evaluation Board
Detailed Description Table 1-10 GTP SMA Clock Connections
SMA Pin
Schematic Net Name
U1 FPGA Pin
Table 1-11 PCIe Edge Connector Connections
P4 PCIe Edge Connector
9. PCI Express Endpoint Connectivity
Chapter 1 SP605 Evaluation Board
References
Detailed Description
Product information
10. SFP Module Connector
SFP Control/Status Signal
P2 SFP Module Connector
Table 1-12 SFP Module Control and Status
Table 1-14 PHY Configuration Pins
11. 10/100/1000 Tri-Speed Ethernet PHY
Bit2
Bit1
Table 1-15 Ethernet PHY Connections Cont’d
References
Chapter 1 SP605 Evaluation Board
U1 FPGA Pin
Table 1-16 USB Type B Pin Assignments and Signal Definitions
USB Connector
12. USB-to-UART Bridge
Description
Schematic Net
13. DVI CODEC
Table 1-18 DVI Controller Connections
U31 Chrontel CH7301C
14. IIC Bus
Figure 1-11 IIC Bus Topology
Detailed Description
Schematic
External Access
8-Kb NV Memory
Table 1-19 IIC Bus Connections
Schematic Netname
Detailed Description Table 1-20 IIC Memory Connections
IIC Memory U4
References
15. Status LEDs
Table 1-21 Status LEDs
Color
Label
Direction Indicator DUP TX RX
Ethernet PHY Status LEDs
Link Rate Mbps
100 1000 P1
FPGA INIT and DONE LEDs
VCC2V5
FPGAINITB
FPGADONE
User LEDs User Pushbutton Switches User DIP Switch User SIP Header
16. User I/O
User LEDs
User SMA GPIO
User Pushbutton Switches
Figure 1-16 User Pushbutton Switch Typical
Table 1-24 Pushbutton Switch Connections
Switch Pin
User DIP Switch
Figure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch Connections
DIP Switch Pin
Schematic Net Name
User SIP Header
Figure 1-18 User SIP Header J55
Table 1-26 User SIP Header Connections
Schematic Net Name
User SMA GPIO
Figure 1-19 User SMA GPIO
Table 1-27 User SMA Connections
GPIO SMA Pin
17. Switches
Power On/Off Slide Switch SW2
Power On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low
SYSACERESETB Pushbutton SW9 Active-Low
SYSACERESETB Pushbutton SW9 Active-Low
Figure 1-22 System ACE CF RESETB Pushbutton SW9
FPGAPROGB Pushbutton SW3 Active-Low
Figure 1-21 FPGA PROGB Pushbutton SW3
System ACE CF CompactFlash Image Select DIP Switch S1 Active-High
Figure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1
SDMX-4-X
Chapter 1 SP605 Evaluation Board
Mode DIP Switch SW1 Active-High
Figure 1-24 FPGA Mode DIP Switch SW1
R9 SDMX-2-X
References
18. VITA 57.1 FMC LPC Connector
Chapter 1 SP605 Evaluation Board
Table 1-28 VITA 57.1 FMC LPC Connections
J63 FMC
LPC Pin
Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”
Power Management
AC Adapter and 12V Input Power Jack/Switch
Table 1-28 VITA 57.1 FMC LPC Connections Cont’d
Schematic Net Name
Onboard Power Regulation
Power Management
Power Supply
Figure 1-25 Onboard Power Regulators
Table 1-29 Onboard Power System Devices
Power Rail Net
Device Type
Reference
Configuration Options
Configuration Options
“5. System ACE CF and CompactFlash Connector,” page
Table 1-30 SP605 FPGA Configuration Modes
Chapter 1 SP605 Evaluation Board
SP605 Hardware User Guide
UG526 v1.1.1 February 1
Default Jumper and Switch Settings
Table A-1 Default Switch Settings
Default
Appendix A
Appendix A Default Jumper and Switch Settings
Table A-2 Default Jumper Settings
CF Error LED
Jumper
VITA 57.1 FMC LPC Connector Pinout
Figure B-1 FMC LPC Connector Pinout
Appendix B
UG526 v1.1.1 February 1
Appendix B VITA 57.1 FMC LPC Connector Pinout
SP605 Hardware User Guide
UG526 v1.1.1 February 1
SP605 Master UCF
Appendix C
UG526 v1.1.1 February 1
Appendix C SP605 Master UCF
SP605 Hardware User Guide
UG526 v1.1.1 February 1
UG526 v1.1.1 February 1
LOC = AA20
Appendix C SP605 Master UCF
3. Series resistors are included
Appendix C SP605 Master UCF
SP605 Hardware User Guide
UG526 v1.1.1 February 1
References
Appendix D