PHYRXD7 | Xilinx SP605 specification

Chapter 1: SP605 Evaluation Board

Table 1-15:Ethernet PHY Connections (Cont’d)

	U1 FPGA Pin	Schematic Net Name	U46 M88E111

			Pin Number	Pin Name
			Pin Number	Pin Name

	U22	PHY_RXD7	120	RXD7

	AB7	PHY_TXC_GTPCLK	14	GTXCLK

	L20	PHY_TXCLK	10	TXCLK

	U8	PHY_TXER	13	TXER

	T8	PHY_TXCTL_TXEN	16	TXEN

	U10	PHY_TXD0	18	TXD0

	T10	PHY_TXD1	19	TXD1

	AB8	PHY_TXD2	20	TXD2

	AA8	PHY_TXD3	24	TXD3

	AB9	PHY_TXD4	25	TXD4

	Y9	PHY_TXD5	26	TXD5

	Y12	PHY_TXD6	28	TXD6

	W12	PHY_TXD7	29	TXD7

References

See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information. [Ref 17]

Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide. [Ref 7]

32	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

Image 32

Xilinx SP605 manual PHYRXD7

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optional Revision History Date Version Revision Table of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide SP605 Evaluation Board Additional Information Features SP605 Evaluation Board Block Diagram Overview SP605 Features Feature Detailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d MB DDR3 Component Memory Voltage RailsDetailed Description 2I/O Voltage Rail of Fpga Banks Schematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory Connections U1 Fpga SPI x4 Flash 3J17 SPI Flash Programming Header Schematic Net Name Detailed Description 6SPI x4 Memory Connections Linear BPI Flash Pin Number Pin Name FLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144I USB Jtag Clock Generation Oscillator Differential Oscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential Multi-Gigabit Transceivers GTP MGTs MGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References SFP Module Connector Sfpclkqop 14PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga Pin PHYRXD7 USB-to-UART Bridge 17 USB-to-UART Connections DVI Codec IIC Bus 11IIC Bus Topology Kb NV Memory Iicsclsfp Iicsdamain SDA Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 13Ethernet PHY Status LEDs Fpga Init and Done LEDs 22 Fpga Init and Done LED Connections User I/O User LEDs23User LED Connections U1 Fpga Pin Controlled LED User Pushbutton Switches SW6 User DIP Switch User SIP Header U1 Fpga Pin User SMA Gpio Usersmagpion Usersmagpiop Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1 Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and 12V Input Power Jack/Switch Onboard Power Regulation Power Management UCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Table A-1Default Switch Settings Function/Type Default FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET Fmcpwrgoodflashrstb NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References