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Xilinx SP605 manual 28 VITA 57.1 FMC LPC Connections, J63 FMC, LPC Pin, Detailed Description

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Table 1-28:VITA 57.1 FMC LPC Connections

							Detailed Description

			Table 1-28shows the VITA 57.1 FMC LPC connections. The connector pinout is in
			Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”
Table 1-28:VITA 57.1 FMC LPC Connections

J63 FMC			Schematic Net Name	U1 FPGA		J63 FMC	Schematic Net Name	U1 FPGA
LPC Pin			Schematic Net Name	Pin		LPC Pin	Schematic Net Name	Pin
LPC Pin				Pin		LPC Pin		Pin

						D1	FMC_PWR_GOOD_FLASH_RST_B	V13

C2			FMC_DP0_C2M_P	B16		D4	FMC_GBTCLK0_M2C_P	E12

C3			FMC_DP0_C2M_N	A16		D5	FMC_GBTCLK0_M2C_N	F12

C6			FMC_DP0_M2C_P	D15		D8	FMC_LA01_CC_P	F14

C7			FMC_DP0_M2C_N	C15		D9	FMC_LA01_CC_N	F15

C10			FMC_LA06_P	D4		D11	FMC_LA05_P	C4

C11			FMC_LA06_N	D5		D12	FMC_LA05_N	A4

C14			FMC_LA10_P	H10		D14	FMC_LA09_P	F7

C15			FMC_LA10_N	H11		D15	FMC_LA09_N	F8

C18			FMC_LA14_P	C17		D17	FMC_LA13_P	G16

C19			FMC_LA14_N	A17		D18	FMC_LA13_N	F17

C22			FMC_LA18_CC_P	T12		D20	FMC_LA17_CC_P	Y11

C23			FMC_LA18_CC_N	U12		D21	FMC_LA17_CC_N	AB11

C26			FMC_LA27_P	AA10		D23	FMC_LA23_P	U9

C27			FMC_LA27_N	AB10		D24	FMC_LA23_N	V9

C30			IIC_SCL_MAIN	T21		D26	FMC_LA26_P	U14

C31			IIC_SDA_MAIN	R22		D27	FMC_LA26_N	U13


G2			FMC_CLK1_M2C_P	E16		H2	FMC_PRSNT_M2C_L	Y16

G3			FMC_CLK1_M2C_N	F16		H4	FMC_CLK0_M2C_P	H12

G6			FMC_LA00_CC_P	H10		H5	FMC_CLK0_M2C_N	G11

G7			FMC_LA00_CC_N	H11		H7	FMC_LA02_P	G8

G9			FMC_LA03_P	B18		H8	FMC_LA02_N	F9

G10			FMC_LA03_N	A18		H10	FMC_LA04_P	C19

G12			FMC_LA08_P	B20		H11	FMC_LA04_N	A19

G13			FMC_LA08_N	A20		H13	FMC_LA07_P	B2

G15			FMC_LA12_P	H13		H14	FMC_LA07_N	A2

G16			FMC_LA12_N	G13		H16	FMC_LA11_P	H14

G18			FMC_LA16_P	C5		H17	FMC_LA11_N	G15

G19			FMC_LA16_N	A5		H19	FMC_LA15_P	D18

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Xilinx SP605 manual 28 VITA 57.1 FMC LPC Connections, J63 FMC, LPC Pin, Detailed Description

Contents

UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideGuide Subtitle optional Version Updated Figure 1-17 and FigureRevision History DateTable of Contents Preface About This GuideChapter 1 SP605 Evaluation Board Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC Connector Appendix A Default Jumper and Switch SettingsAppendix B VITA 57.1 FMC LPC Connector Pinout Appendix C SP605 Master UCF Appendix D ReferencesAbout This Guide Guide ContentsAppendix A, “Default Jumper and Switch Settings.” Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardChapter OverviewChapter 1 SP605 Evaluation Board Features5. System ACE CF and CompactFlash Connector 6. USB JTAG 10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY4. Linear BPI Flash 5. System ACE CF and CompactFlash Connector Block Diagram17. Switches 18. VITA 57.1 FMC LPC Connector Configuration OptionsDetailed Description SP605 FeaturesFeature Related Xilinx DocumentsLinear BPI Flash SP605 Features Cont’dDetailed Description FeatureSP605 Features Cont’d Configuration1. Spartan-6 XC6SLX45T-3FGG484 FPGA ReferencesTable 1-2 I/O Voltage Rail of FPGA Banks Signal Name2. 128 MB DDR3 Component Memory I/O Voltage RailsFPGA Pin Number Schematic Net NameTable 1-4 FPGA On-Chip OCT Termination External Resistor Requirements U1 FPGA PinMemory U42 DDR3 Component Memory Connections Cont’dReferences Detailed DescriptionFigure 1-4 SPI Flash Interface Topology 3. SPI x4 FlashSilkscreen Figure 1-3 J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description Table 1-6 SPI x4 Memory ConnectionsSPI MEM U32 SPI HDR J17U25 BPI FLASH 4. Linear BPI FlashFigure 1-5 Linear BPI Flash Interface Table 1-7 Linear Flash ConnectionsU25 BPI FLASH Detailed Description Table 1-7 Linear Flash Connections Cont’dSchematic Net Name U1 FPGA PinChapter 1 SP605 Evaluation Board 5. System ACE CF and CompactFlash ConnectorFPGA Design Considerations for the Configuration Flash ReferencesDetailed Description Schematic Net Name1Table 1-8 System ACE CF Connections U17 XCCACETQ144ISchematic Net Name Figure 1-6 JTAG Chain Diagram6. USB JTAG Table 1-8 System ACE CF Connections Cont’dReferences 7. Clock GenerationOscillator Differential Figure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19Silkscreened outline has beveled corner Socket has notch in crossbar Oscillator Socket Single-Ended, 2.5V orFigure 1-8 SP605 X2 Oscillator Socket Pin 1 Location Identifiers Figure 1-9 SP605 X2 Oscillator Pin 1 Location IdentifiersSource SMA Connectors Differential8. Multi-Gigabit Transceivers GTP MGTs Table 1-9 SP605 Clock Source ConnectionsChapter 1 SP605 Evaluation Board Figure 1-10 GTP SMA ClockSMA MGT Connectors MGT REFCLKU1 FPGA Pin Detailed Description Table 1-10 GTP SMA Clock ConnectionsSMA Pin Schematic Net NameChapter 1 SP605 Evaluation Board Table 1-11 PCIe Edge Connector ConnectionsP4 PCIe Edge Connector 9. PCI Express Endpoint ConnectivityReferences Detailed DescriptionProduct information Table 1-12 SFP Module Control and Status 10. SFP Module ConnectorSFP Control/Status Signal P2 SFP Module ConnectorBit1 Table 1-14 PHY Configuration Pins11. 10/100/1000 Tri-Speed Ethernet PHY Bit2U1 FPGA Pin Table 1-15 Ethernet PHY Connections Cont’dReferences Chapter 1 SP605 Evaluation BoardDescription Table 1-16 USB Type B Pin Assignments and Signal DefinitionsUSB Connector 12. USB-to-UART BridgeU31 Chrontel CH7301C Schematic Net13. DVI CODEC Table 1-18 DVI Controller Connections14. IIC Bus Figure 1-11 IIC Bus TopologyDetailed Description Table 1-19 IIC Bus Connections SchematicExternal Access 8-Kb NV MemoryReferences Schematic NetnameDetailed Description Table 1-20 IIC Memory Connections IIC Memory U4Label 15. Status LEDsTable 1-21 Status LEDs Color100 1000 P1 Direction Indicator DUP TX RXEthernet PHY Status LEDs Link Rate MbpsFPGADONE FPGA INIT and DONE LEDsVCC2V5 FPGAINITBUser SMA GPIO User LEDs User Pushbutton Switches User DIP Switch User SIP Header16. User I/O User LEDsSwitch Pin User Pushbutton SwitchesFigure 1-16 User Pushbutton Switch Typical Table 1-24 Pushbutton Switch ConnectionsSchematic Net Name User DIP SwitchFigure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch Connections DIP Switch PinSchematic Net Name User SIP HeaderFigure 1-18 User SIP Header J55 Table 1-26 User SIP Header ConnectionsGPIO SMA Pin User SMA GPIOFigure 1-19 User SMA GPIO Table 1-27 User SMA ConnectionsSYSACERESETB Pushbutton SW9 Active-Low 17. SwitchesPower On/Off Slide Switch SW2 Power On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-LowFigure 1-21 FPGA PROGB Pushbutton SW3 SYSACERESETB Pushbutton SW9 Active-LowFigure 1-22 System ACE CF RESETB Pushbutton SW9 FPGAPROGB Pushbutton SW3 Active-LowChapter 1 SP605 Evaluation Board System ACE CF CompactFlash Image Select DIP Switch S1 Active-HighFigure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1 SDMX-4-XReferences Mode DIP Switch SW1 Active-HighFigure 1-24 FPGA Mode DIP Switch SW1 R9 SDMX-2-XChapter 1 SP605 Evaluation Board 18. VITA 57.1 FMC LPC ConnectorAppendix B, “VITA 57.1 FMC LPC Connector Pinout.” Table 1-28 VITA 57.1 FMC LPC ConnectionsJ63 FMC LPC PinSchematic Net Name Power ManagementAC Adapter and 12V Input Power Jack/Switch Table 1-28 VITA 57.1 FMC LPC Connections Cont’dFigure 1-25 Onboard Power Regulators Onboard Power RegulationPower Management Power SupplyReference Table 1-29 Onboard Power System DevicesPower Rail Net Device TypeTable 1-30 SP605 FPGA Configuration Modes Configuration OptionsConfiguration Options “5. System ACE CF and CompactFlash Connector,” pageChapter 1 SP605 Evaluation Board SP605 Hardware User GuideUG526 v1.1.1 February 1 Appendix A Default Jumper and Switch SettingsTable A-1 Default Switch Settings DefaultJumper Appendix A Default Jumper and Switch SettingsTable A-2 Default Jumper Settings CF Error LEDUG526 v1.1.1 February 1 VITA 57.1 FMC LPC Connector PinoutFigure B-1 FMC LPC Connector Pinout Appendix BAppendix B VITA 57.1 FMC LPC Connector Pinout SP605 Hardware User GuideUG526 v1.1.1 February 1 SP605 Master UCF Appendix CUG526 v1.1.1 February 1 Appendix C SP605 Master UCF SP605 Hardware User GuideUG526 v1.1.1 February 1 LOC = AA20 UG526 v1.1.1 February 1Appendix C SP605 Master UCF 3. Series resistors are included Appendix C SP605 Master UCF SP605 Hardware User GuideUG526 v1.1.1 February 1 Appendix D References