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Xilinx SP605 manual 11 IIC Bus Topology, Detailed Description

Models: SP605

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14. IIC Bus

14. IIC Bus

Detailed Description

U1

BANK 1

IICFPGA INTERFACE	BANK 0
	BANK 0
	BANK 2

P3

DVI Connector

Addr: 0b1010000

The SP605 implements three IIC bus interfaces at the FPGA.

The MAIN IIC bus hosts four items:

•FPGA U1 Bank 1 "MAIN" IIC interface

•8-Kb NV Memory U4

•FMC LPC connector J2

•2-Pin External Access Header J45

The DVI IIC bus hosts two items:

•FPGA U1 Bank 2 DVI IIC interface

•DVI Codec U31 and DVI connector P3 The SFP IIC bus hosts two items:

•FPGA U1 Bank 0 SFP IIC interface

•SFP module connector P2

The SP605 IIC bus topology is shown in Figure 1-11.

IIC_SDA_MAIN

IIC_SCL_MAIN

IIC_SDA_SFP

IIC_SCL_SFP

IIC_SDA_DVI

IIC_SCL_DVI

LEVEL

SHIFTER

IIC_CLK_DVI_F

IIC_SDA_DVI_F

U4

ST MICRO

M24C08-WDW6TP

Addr: 0b1010100 through

0b1010111

J2

FMC LPC

Column C

2 Kb EEPROM on

any FMC LPC

Mezzanine Card Addr: 0b1010010

J45

2-Pin External Access Header

U31

DVI CODEC

CHRONTEL

CH730C-TF

Addr: 0b1110110

Figure 1-11:IIC Bus Topology

SP605 Hardware User Guide

www.xilinx.com

UG526 (v1.1.1) February 1, 2010

P2

SFP Module

Connector

Addr: 0b1010000

UG526_11_092609

35

Image 35

Xilinx SP605 manual 11 IIC Bus Topology, Detailed Description

Contents

Guide Subtitle optional UG526 v1.1.1 February 1, 2010 optionalSP605 Hardware User Guide Version Updated Figure 1-17 and FigureRevision History DateChapter 1 SP605 Evaluation Board Table of ContentsPreface About This Guide Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC Connector Appendix A Default Jumper and Switch SettingsAppendix B VITA 57.1 FMC LPC Connector Pinout Appendix C SP605 Master UCF Appendix D ReferencesAbout This Guide Guide ContentsAppendix A, “Default Jumper and Switch Settings.” Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardChapter OverviewChapter 1 SP605 Evaluation Board Features5. System ACE CF and CompactFlash Connector 6. USB JTAG 10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY4. Linear BPI Flash 5. System ACE CF and CompactFlash Connector Block Diagram17. Switches 18. VITA 57.1 FMC LPC Connector Configuration OptionsDetailed Description SP605 FeaturesFeature Related Xilinx DocumentsLinear BPI Flash SP605 Features Cont’dDetailed Description FeatureSP605 Features Cont’d Configuration1. Spartan-6 XC6SLX45T-3FGG484 FPGA ReferencesTable 1-2 I/O Voltage Rail of FPGA Banks Signal Name2. 128 MB DDR3 Component Memory I/O Voltage RailsFPGA Pin Number Schematic Net NameTable 1-4 FPGA On-Chip OCT Termination External Resistor Requirements U1 FPGA PinMemory U42 DDR3 Component Memory Connections Cont’dReferences Detailed DescriptionFigure 1-4 SPI Flash Interface Topology 3. SPI x4 FlashSilkscreen Figure 1-3 J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description Table 1-6 SPI x4 Memory ConnectionsSPI MEM U32 SPI HDR J17U25 BPI FLASH 4. Linear BPI FlashFigure 1-5 Linear BPI Flash Interface Table 1-7 Linear Flash ConnectionsU25 BPI FLASH Detailed Description Table 1-7 Linear Flash Connections Cont’dSchematic Net Name U1 FPGA PinChapter 1 SP605 Evaluation Board 5. System ACE CF and CompactFlash ConnectorFPGA Design Considerations for the Configuration Flash ReferencesDetailed Description Schematic Net Name1Table 1-8 System ACE CF Connections U17 XCCACETQ144ISchematic Net Name Figure 1-6 JTAG Chain Diagram6. USB JTAG Table 1-8 System ACE CF Connections Cont’dReferences 7. Clock GenerationOscillator Differential Figure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19Silkscreened outline has beveled corner Socket has notch in crossbar Oscillator Socket Single-Ended, 2.5V orFigure 1-8 SP605 X2 Oscillator Socket Pin 1 Location Identifiers Figure 1-9 SP605 X2 Oscillator Pin 1 Location IdentifiersSource SMA Connectors Differential8. Multi-Gigabit Transceivers GTP MGTs Table 1-9 SP605 Clock Source ConnectionsChapter 1 SP605 Evaluation Board Figure 1-10 GTP SMA ClockSMA MGT Connectors MGT REFCLKU1 FPGA Pin Detailed Description Table 1-10 GTP SMA Clock ConnectionsSMA Pin Schematic Net NameChapter 1 SP605 Evaluation Board Table 1-11 PCIe Edge Connector ConnectionsP4 PCIe Edge Connector 9. PCI Express Endpoint ConnectivityProduct information ReferencesDetailed Description Table 1-12 SFP Module Control and Status 10. SFP Module ConnectorSFP Control/Status Signal P2 SFP Module ConnectorBit1 Table 1-14 PHY Configuration Pins11. 10/100/1000 Tri-Speed Ethernet PHY Bit2U1 FPGA Pin Table 1-15 Ethernet PHY Connections Cont’dReferences Chapter 1 SP605 Evaluation BoardDescription Table 1-16 USB Type B Pin Assignments and Signal DefinitionsUSB Connector 12. USB-to-UART BridgeU31 Chrontel CH7301C Schematic Net13. DVI CODEC Table 1-18 DVI Controller ConnectionsDetailed Description 14. IIC BusFigure 1-11 IIC Bus Topology Table 1-19 IIC Bus Connections SchematicExternal Access 8-Kb NV MemoryReferences Schematic NetnameDetailed Description Table 1-20 IIC Memory Connections IIC Memory U4Label 15. Status LEDsTable 1-21 Status LEDs Color100 1000 P1 Direction Indicator DUP TX RXEthernet PHY Status LEDs Link Rate MbpsFPGADONE FPGA INIT and DONE LEDsVCC2V5 FPGAINITBUser SMA GPIO User LEDs User Pushbutton Switches User DIP Switch User SIP Header16. User I/O User LEDsSwitch Pin User Pushbutton SwitchesFigure 1-16 User Pushbutton Switch Typical Table 1-24 Pushbutton Switch ConnectionsSchematic Net Name User DIP SwitchFigure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch Connections DIP Switch PinSchematic Net Name User SIP HeaderFigure 1-18 User SIP Header J55 Table 1-26 User SIP Header ConnectionsGPIO SMA Pin User SMA GPIOFigure 1-19 User SMA GPIO Table 1-27 User SMA ConnectionsSYSACERESETB Pushbutton SW9 Active-Low 17. SwitchesPower On/Off Slide Switch SW2 Power On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-LowFigure 1-21 FPGA PROGB Pushbutton SW3 SYSACERESETB Pushbutton SW9 Active-LowFigure 1-22 System ACE CF RESETB Pushbutton SW9 FPGAPROGB Pushbutton SW3 Active-LowChapter 1 SP605 Evaluation Board System ACE CF CompactFlash Image Select DIP Switch S1 Active-HighFigure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1 SDMX-4-XReferences Mode DIP Switch SW1 Active-HighFigure 1-24 FPGA Mode DIP Switch SW1 R9 SDMX-2-XChapter 1 SP605 Evaluation Board 18. VITA 57.1 FMC LPC ConnectorAppendix B, “VITA 57.1 FMC LPC Connector Pinout.” Table 1-28 VITA 57.1 FMC LPC ConnectionsJ63 FMC LPC PinSchematic Net Name Power ManagementAC Adapter and 12V Input Power Jack/Switch Table 1-28 VITA 57.1 FMC LPC Connections Cont’dFigure 1-25 Onboard Power Regulators Onboard Power RegulationPower Management Power SupplyReference Table 1-29 Onboard Power System DevicesPower Rail Net Device TypeTable 1-30 SP605 FPGA Configuration Modes Configuration OptionsConfiguration Options “5. System ACE CF and CompactFlash Connector,” pageUG526 v1.1.1 February 1 Chapter 1 SP605 Evaluation BoardSP605 Hardware User Guide Appendix A Default Jumper and Switch SettingsTable A-1 Default Switch Settings DefaultJumper Appendix A Default Jumper and Switch SettingsTable A-2 Default Jumper Settings CF Error LEDUG526 v1.1.1 February 1 VITA 57.1 FMC LPC Connector PinoutFigure B-1 FMC LPC Connector Pinout Appendix BUG526 v1.1.1 February 1 Appendix B VITA 57.1 FMC LPC Connector PinoutSP605 Hardware User Guide UG526 v1.1.1 February 1 SP605 Master UCFAppendix C UG526 v1.1.1 February 1 Appendix C SP605 Master UCFSP605 Hardware User Guide LOC = AA20 UG526 v1.1.1 February 1Appendix C SP605 Master UCF 3. Series resistors are included UG526 v1.1.1 February 1 Appendix C SP605 Master UCFSP605 Hardware User Guide Appendix D References