11IIC Bus Topology | Xilinx SP605 manual

14. IIC Bus

Detailed Description

U1

BANK 1

IICFPGA INTERFACE	BANK 0
	BANK 0
	BANK 2

P3

DVI Connector

Addr: 0b1010000

The SP605 implements three IIC bus interfaces at the FPGA.

The MAIN IIC bus hosts four items:

•FPGA U1 Bank 1 "MAIN" IIC interface

•8-Kb NV Memory U4

•FMC LPC connector J2

•2-Pin External Access Header J45

The DVI IIC bus hosts two items:

•FPGA U1 Bank 2 DVI IIC interface

•DVI Codec U31 and DVI connector P3 The SFP IIC bus hosts two items:

•FPGA U1 Bank 0 SFP IIC interface

•SFP module connector P2

The SP605 IIC bus topology is shown in Figure 1-11.

IIC_SDA_MAIN

IIC_SCL_MAIN

IIC_SDA_SFP

IIC_SCL_SFP

IIC_SDA_DVI

IIC_SCL_DVI

LEVEL

SHIFTER

IIC_CLK_DVI_F

IIC_SDA_DVI_F

U4

ST MICRO

M24C08-WDW6TP

Addr: 0b1010100 through

0b1010111

J2

FMC LPC

Column C

2 Kb EEPROM on

any FMC LPC

Mezzanine Card Addr: 0b1010010

J45

2-Pin External Access Header

U31

DVI CODEC

CHRONTEL

CH730C-TF

Addr: 0b1110110

Figure 1-11:IIC Bus Topology

SP605 Hardware User Guide

www.xilinx.com

UG526 (v1.1.1) February 1, 2010

P2

SFP Module

Connector

Addr: 0b1010000

UG526_11_092609

35

Image 35

Xilinx SP605 manual 11IIC Bus Topology

Contents

UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User Guide Date Version Revision Revision History Table of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information SP605 Evaluation Board SP605 Evaluation Board Features Overview Block Diagram Feature SP605 Features Detailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d 2I/O Voltage Rail of Fpga Banks MB DDR3 Component MemoryVoltage Rails Detailed Description 5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin Name U1 Fpga 3J17 SPI Flash Programming Header SPI x4 Flash Detailed Description 6SPI x4 Memory Connections Schematic Net Name Pin Number Pin Name Linear BPI Flash FLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector U17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 USB Jtag Oscillator Differential Clock Generation 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V or Multi-Gigabit Transceivers GTP MGTs SMA Connectors Differential MGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References Sfpclkqop SFP Module Connector 15Ethernet PHY Connections U1 Fpga Pin 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 PHYRXD7 17 USB-to-UART Connections USB-to-UART Bridge DVI Codec 11IIC Bus Topology IIC Bus Iicsclsfp Kb NV Memory Iicsdamain SDA Status LEDs Signal Name Color Label Description 13Ethernet PHY Status LEDs Ethernet PHY Status LEDs 22 Fpga Init and Done LED Connections Fpga Init and Done LEDs Controlled LED User I/OUser LEDs 23User LED Connections U1 Fpga Pin SW6 User Pushbutton Switches User DIP Switch U1 Fpga Pin User SIP Header Usersmagpion Usersmagpiop User SMA Gpio Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-High Vita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC Connections AC Adapter and 12V Input Power Jack/Switch Power Management Power Management Onboard Power Regulation UCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Function/Type Default Table A-1Default Switch Settings FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCF NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References