MGT Refclk | Xilinx SP605 instruction

Chapter 1: SP605 Evaluation Board

C33 1

SMA_RX_N

SMA_RX_P

C34 1

SMA MGT Connectors

SMA_TX_N

SMA_TX_P

0.1UF

0.1UF

				J35		32K10K-400E3
								2
							GND1	2
							GND1	3
							GND2	3
							GND2	4
	2						GND3	4
		SMA_RX_C_N	1		SIG		GND3	5
							GND4

								6
		X5R					GND5	6
	10V						GND5	7
	10V						GND6	7
							GND6	8
							GND7	8
							GND7
				J34		32K10K-400E3
								2
							GND1	2
							GND1	3
							GND2	3
							GND2	4
	2						GND3	4
		SMA_RX_C_P	1				GND3	5
					SIG		GND4

								6
		X5R					GND5	6
	10V						GND5	7
	10V						GND6	7
							GND6	8
							GND7	8
							GND7
				J33		32K10K-400E3



								2
							GND1	2
							GND1	3
							GND2	3
							GND2	4
							GND3	4
			1				GND3	5
			1		SIG		GND4	5
					SIG		GND4	6
							GND5	6
							GND5	7
							GND6	7
							GND6	8
							GND7	8
							GND7
				J32		32K10K-400E3
								2
							GND1	2
							GND1	3
							GND2	3
							GND2	4
							GND3	4
			1		SIG		GND3	5
			1				GND4	5
							GND4	6
							GND5	6
							GND5	7
							GND6	7
							GND6	8
							GND7	8
							GND7

MGT REFCLK

SMA_REFCLK_N

SMA_REFCLK_P

C35 1

C36 1

0.1UF

0.1UF

2
10V	X5R

2
10V	X5R

	J36		32K10K-400E3
					2
				GND1	2
				GND1	3
				GND2	3
				GND2	4
				GND3	4
SMA_REFCLK_C_N 1				GND3	5
SMA_REFCLK_C_N 1		SIG		GND4	5
		SIG		GND4	6
				GND5	6
				GND5	7
				GND6	7
				GND6	8
				GND7	8
				GND7
	J37		32K10K-400E3
					2
				GND1	2
				GND1	3
				GND2	3
				GND2	4
				GND3	4
SMA_REFCLK_C_P 1				GND3	5
SMA_REFCLK_C_P 1		SIG		GND4	5
		SIG		GND4	6
				GND5	6
				GND5	7
				GND6	7
				GND6	8
				GND7	8
				GND7

UG526_10 _092409

Figure 1-10: GTP SMA Clock

26	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

Image 26

Xilinx SP605 manual MGT Refclk

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optional Revision History Date Version Revision Table of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide SP605 Evaluation Board Additional Information Features SP605 Evaluation Board Block Diagram Overview SP605 Features Feature Detailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga Banks Schematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory Connections U1 Fpga SPI x4 Flash 3J17 SPI Flash Programming Header Schematic Net Name Detailed Description 6SPI x4 Memory Connections Linear BPI Flash Pin Number Pin Name FLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144I USB Jtag Clock Generation Oscillator Differential Oscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential Multi-Gigabit Transceivers GTP MGTs MGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References SFP Module Connector Sfpclkqop Bit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga Pin PHYRXD7 USB-to-UART Bridge 17 USB-to-UART Connections DVI Codec IIC Bus 11IIC Bus Topology Kb NV Memory Iicsclsfp Iicsdamain SDA Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 13Ethernet PHY Status LEDs Fpga Init and Done LEDs 22 Fpga Init and Done LED Connections 23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LED User Pushbutton Switches SW6 User DIP Switch User SIP Header U1 Fpga Pin User SMA Gpio Usersmagpion Usersmagpiop Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1 Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and 12V Input Power Jack/Switch Onboard Power Regulation Power Management UCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Table A-1Default Switch Settings Function/Type Default FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET Fmcpwrgoodflashrstb NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References