5DDR3 Component Memory Connections | Xilinx SP605 guide

Chapter 1: SP605 Evaluation Board

Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements

U1 FPGA Pin	FPGA Pin Number	Board Connection for OCT

ZIO	P3	No Connect

RZQ	L6	100 ohms to GROUND

Table 1-5shows the connections and pin numbers for the DDR3 Component Memory.

Table 1-5:DDR3 Component Memory Connections

U1 FPGA	Schematic Net Name	Memory U42
U1 FPGA
Pin		Pin Number		Pin Name
Pin


K2	MEM1_A0	N3		A0

K1	MEM1_A1	P7		A1

K5	MEM1_A2	P3		A2

M6	MEM1_A3	N2		A3

H3	MEM1_A4	P8		A4

M3	MEM1_A5	P2		A5

L4	MEM1_A6	R8		A6

K6	MEM1_A7	R2		A7

G3	MEM1_A8	T8		A8

G1	MEM1_A9	R3		A9

J4	MEM1_A10	L7		A10/AP

E1	MEM1_A11	R7		A11

F1	MEM1_A12	N7		A12/BCN

J6	MEM1_A13	T3		NC/A13

H5	MEM1_A14	T7		NC/A14

J3	MEM1_BA0	M2		BA0

J1	MEM1_BA1	N8		BA1

H1	MEM1_BA2	M3		BA2


R3	MEM1_DQ0	G2		DQ6

R1	MEM1_DQ1	H3		DQ4

P2	MEM1_DQ2	E3		DQ0

P1	MEM1_DQ3	F2		DQ2

L3	MEM1_DQ4	H7		DQ7

L1	MEM1_DQ5	H8		DQ5

M2	MEM1_DQ6	F7		DQ1

M1	MEM1_DQ7	F8		DQ3

T2	MEM1_DQ8	C2		DQ11

14	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

Image 14

Xilinx SP605 manual 5DDR3 Component Memory Connections, Schematic Net Name Memory U42 Pin Pin Number Pin Name

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optional Revision History Date Version Revision Table of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide SP605 Evaluation Board Additional Information Features SP605 Evaluation Board Block Diagram Overview SP605 Features Feature Detailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga Banks Schematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory Connections U1 Fpga SPI x4 Flash 3J17 SPI Flash Programming Header Schematic Net Name Detailed Description 6SPI x4 Memory Connections Linear BPI Flash Pin Number Pin Name FLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144I USB Jtag Clock Generation Oscillator Differential Oscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential Multi-Gigabit Transceivers GTP MGTs MGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References SFP Module Connector Sfpclkqop Bit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga Pin PHYRXD7 USB-to-UART Bridge 17 USB-to-UART Connections DVI Codec IIC Bus 11IIC Bus Topology Kb NV Memory Iicsclsfp Iicsdamain SDA Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 13Ethernet PHY Status LEDs Fpga Init and Done LEDs 22 Fpga Init and Done LED Connections 23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LED User Pushbutton Switches SW6 User DIP Switch User SIP Header U1 Fpga Pin User SMA Gpio Usersmagpion Usersmagpiop Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1 Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and 12V Input Power Jack/Switch Onboard Power Regulation Power Management UCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Table A-1Default Switch Settings Function/Type Default FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET Fmcpwrgoodflashrstb NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References