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Xilinx SP605 4 FPGA On-Chip OCT Termination External Resistor Requirements, U1 FPGA Pin, Pin Name

Models: SP605

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Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements

Chapter 1: SP605 Evaluation Board

Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements

U1 FPGA Pin	FPGA Pin Number	Board Connection for OCT

ZIO	P3	No Connect

RZQ	L6	100 ohms to GROUND

Table 1-5shows the connections and pin numbers for the DDR3 Component Memory.

Table 1-5:DDR3 Component Memory Connections

U1 FPGA	Schematic Net Name	Memory U42
U1 FPGA
Pin		Pin Number		Pin Name
Pin


K2	MEM1_A0	N3		A0

K1	MEM1_A1	P7		A1

K5	MEM1_A2	P3		A2

M6	MEM1_A3	N2		A3

H3	MEM1_A4	P8		A4

M3	MEM1_A5	P2		A5

L4	MEM1_A6	R8		A6

K6	MEM1_A7	R2		A7

G3	MEM1_A8	T8		A8

G1	MEM1_A9	R3		A9

J4	MEM1_A10	L7		A10/AP

E1	MEM1_A11	R7		A11

F1	MEM1_A12	N7		A12/BCN

J6	MEM1_A13	T3		NC/A13

H5	MEM1_A14	T7		NC/A14

J3	MEM1_BA0	M2		BA0

J1	MEM1_BA1	N8		BA1

H1	MEM1_BA2	M3		BA2


R3	MEM1_DQ0	G2		DQ6

R1	MEM1_DQ1	H3		DQ4

P2	MEM1_DQ2	E3		DQ0

P1	MEM1_DQ3	F2		DQ2

L3	MEM1_DQ4	H7		DQ7

L1	MEM1_DQ5	H8		DQ5

M2	MEM1_DQ6	F7		DQ1

M1	MEM1_DQ7	F8		DQ3

T2	MEM1_DQ8	C2		DQ11

14	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

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Xilinx SP605 manual 4 FPGA On-Chip OCT Termination External Resistor Requirements, U1 FPGA Pin, FPGA Pin Number, Memory U42

Contents

Guide Subtitle optional UG526 v1.1.1 February 1, 2010 optionalSP605 Hardware User Guide Date Updated Figure 1-17 and FigureRevision History VersionChapter 1 SP605 Evaluation Board Table of ContentsPreface About This Guide Appendix C SP605 Master UCF Appendix D References Appendix A Default Jumper and Switch SettingsAppendix B VITA 57.1 FMC LPC Connector Pinout Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC ConnectorAppendix B, “VITA 57.1 FMC LPC Connector Pinout.” Guide ContentsAppendix A, “Default Jumper and Switch Settings.” About This GuideAdditional Support Resources Preface About This GuideOverview SP605 Evaluation BoardChapter Additional Information10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY Features5. System ACE CF and CompactFlash Connector 6. USB JTAG Chapter 1 SP605 Evaluation Board18. VITA 57.1 FMC LPC Connector Configuration Options Block Diagram17. Switches 4. Linear BPI Flash 5. System ACE CF and CompactFlash ConnectorRelated Xilinx Documents SP605 FeaturesFeature Detailed DescriptionFeature SP605 Features Cont’dDetailed Description Linear BPI FlashReferences Configuration1. Spartan-6 XC6SLX45T-3FGG484 FPGA SP605 Features Cont’dI/O Voltage Rails Signal Name2. 128 MB DDR3 Component Memory Table 1-2 I/O Voltage Rail of FPGA BanksU1 FPGA Pin Schematic Net NameTable 1-4 FPGA On-Chip OCT Termination External Resistor Requirements FPGA Pin NumberDetailed Description DDR3 Component Memory Connections Cont’dReferences Memory U42Figure 1-3 J17 SPI Flash Programming Header 3. SPI x4 FlashSilkscreen Figure 1-4 SPI Flash Interface TopologySPI HDR J17 Detailed Description Table 1-6 SPI x4 Memory ConnectionsSPI MEM U32 Schematic Net NameTable 1-7 Linear Flash Connections 4. Linear BPI FlashFigure 1-5 Linear BPI Flash Interface U25 BPI FLASHU1 FPGA Pin Detailed Description Table 1-7 Linear Flash Connections Cont’dSchematic Net Name U25 BPI FLASHReferences 5. System ACE CF and CompactFlash ConnectorFPGA Design Considerations for the Configuration Flash Chapter 1 SP605 Evaluation BoardU17 XCCACETQ144I Schematic Net Name1Table 1-8 System ACE CF Connections Detailed DescriptionTable 1-8 System ACE CF Connections Cont’d Figure 1-6 JTAG Chain Diagram6. USB JTAG Schematic Net NameFigure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19 7. Clock GenerationOscillator Differential ReferencesFigure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orFigure 1-8 SP605 X2 Oscillator Socket Pin 1 Location Identifiers Silkscreened outline has beveled corner Socket has notch in crossbarTable 1-9 SP605 Clock Source Connections SMA Connectors Differential8. Multi-Gigabit Transceivers GTP MGTs SourceMGT REFCLK Figure 1-10 GTP SMA ClockSMA MGT Connectors Chapter 1 SP605 Evaluation BoardSchematic Net Name Detailed Description Table 1-10 GTP SMA Clock ConnectionsSMA Pin U1 FPGA Pin9. PCI Express Endpoint Connectivity Table 1-11 PCIe Edge Connector ConnectionsP4 PCIe Edge Connector Chapter 1 SP605 Evaluation BoardProduct information ReferencesDetailed Description P2 SFP Module Connector 10. SFP Module ConnectorSFP Control/Status Signal Table 1-12 SFP Module Control and StatusBit2 Table 1-14 PHY Configuration Pins11. 10/100/1000 Tri-Speed Ethernet PHY Bit1Chapter 1 SP605 Evaluation Board Table 1-15 Ethernet PHY Connections Cont’dReferences U1 FPGA Pin12. USB-to-UART Bridge Table 1-16 USB Type B Pin Assignments and Signal DefinitionsUSB Connector DescriptionTable 1-18 DVI Controller Connections Schematic Net13. DVI CODEC U31 Chrontel CH7301CDetailed Description 14. IIC BusFigure 1-11 IIC Bus Topology 8-Kb NV Memory SchematicExternal Access Table 1-19 IIC Bus ConnectionsIIC Memory U4 Schematic NetnameDetailed Description Table 1-20 IIC Memory Connections ReferencesColor 15. Status LEDsTable 1-21 Status LEDs LabelLink Rate Mbps Direction Indicator DUP TX RXEthernet PHY Status LEDs 100 1000 P1FPGAINITB FPGA INIT and DONE LEDsVCC2V5 FPGADONEUser LEDs User LEDs User Pushbutton Switches User DIP Switch User SIP Header16. User I/O User SMA GPIOTable 1-24 Pushbutton Switch Connections User Pushbutton SwitchesFigure 1-16 User Pushbutton Switch Typical Switch PinDIP Switch Pin User DIP SwitchFigure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch Connections Schematic Net NameTable 1-26 User SIP Header Connections User SIP HeaderFigure 1-18 User SIP Header J55 Schematic Net NameTable 1-27 User SMA Connections User SMA GPIOFigure 1-19 User SMA GPIO GPIO SMA PinPower On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low 17. SwitchesPower On/Off Slide Switch SW2 SYSACERESETB Pushbutton SW9 Active-LowFPGAPROGB Pushbutton SW3 Active-Low SYSACERESETB Pushbutton SW9 Active-LowFigure 1-22 System ACE CF RESETB Pushbutton SW9 Figure 1-21 FPGA PROGB Pushbutton SW3SDMX-4-X System ACE CF CompactFlash Image Select DIP Switch S1 Active-HighFigure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1 Chapter 1 SP605 Evaluation BoardR9 SDMX-2-X Mode DIP Switch SW1 Active-HighFigure 1-24 FPGA Mode DIP Switch SW1 References18. VITA 57.1 FMC LPC Connector Chapter 1 SP605 Evaluation BoardLPC Pin Table 1-28 VITA 57.1 FMC LPC ConnectionsJ63 FMC Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”Table 1-28 VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and 12V Input Power Jack/Switch Schematic Net NamePower Supply Onboard Power RegulationPower Management Figure 1-25 Onboard Power RegulatorsDevice Type Table 1-29 Onboard Power System DevicesPower Rail Net Reference“5. System ACE CF and CompactFlash Connector,” page Configuration OptionsConfiguration Options Table 1-30 SP605 FPGA Configuration ModesUG526 v1.1.1 February 1 Chapter 1 SP605 Evaluation BoardSP605 Hardware User Guide Default Default Jumper and Switch SettingsTable A-1 Default Switch Settings Appendix ACF Error LED Appendix A Default Jumper and Switch SettingsTable A-2 Default Jumper Settings JumperAppendix B VITA 57.1 FMC LPC Connector PinoutFigure B-1 FMC LPC Connector Pinout UG526 v1.1.1 February 1UG526 v1.1.1 February 1 Appendix B VITA 57.1 FMC LPC Connector PinoutSP605 Hardware User Guide UG526 v1.1.1 February 1 SP605 Master UCFAppendix C UG526 v1.1.1 February 1 Appendix C SP605 Master UCFSP605 Hardware User Guide UG526 v1.1.1 February 1 LOC = AA20Appendix C SP605 Master UCF 3. Series resistors are included UG526 v1.1.1 February 1 Appendix C SP605 Master UCFSP605 Hardware User Guide References Appendix D