Intel IXP46X, IXP45X manual Related Documentation, Title Document #

Page 10

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Introduction

1.2Related Documentation

The reader of this design guide should also be familiar with the material and concepts presented in the following documents:

Title

Document #

 

 

Hardware-Assisted IEEE 1588* Implementation in the Intel® IXP46X

305068

Product Line White Paper

 

 

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

306262

Developer’s Manual

 

 

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

306261

Datasheet

 

 

 

Intel® IXP4XX Product Line of Network Processors Specification

306428

Update

 

 

 

Intel® IXP400 Software Programmer’s Guide

252539

Intel® IXP400 Software Specification Update

273795

Intel® XScale™ Core Developer’s Manual

273473

Intel® IXDP465 Development Platform Documentation Kit

N/A

Intel XScale® Microarchitecture Technical Summary

—

Intel StrataFlash® Memory (J3) to Intel® Embedded Memory (J3

308555

v.D) Conversion Guide - Application Note 835

 

 

 

Migration Guide for Intel StrataFlash® Synchronous Memory (J3) to

 

Intel StrataFlash® Embedded Memory (P30 and P33) - Application

306667

Note 812

 

 

 

Migration Guide for Intel StrataFlash® Synchronous Memory (K3/

 

K18) to Intel StrataFlash® Embedded Memory (P30) - Application

306669

Note 825

 

 

 

Double Data Rate (DDR) SDRAM Specification, 2004; JEDEC Solid

JESD79D

State Technology Association

 

 

 

I2C-Bus Specification from Philips Semiconductors*

Available at http://www.nxp.com

IEEE 802.3 Specification

N/A

 

 

IEEE 1149.1 Specification

N/A

 

 

PCI Local Bus Specification, Rev. 2.2

N/A

 

 

Universal Serial Bus Specification, Revision 1.1

N/A

 

 

UTOPIA Level 2 Specification, Revision 1.0

N/A

 

 

Note: For Intel documentation, see the Intel Technical Documentation Center, available through the following link:

http://www.intel.com/products/index.htm

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

 

HDD

December 2006

10

Document Number: 305261; Revision: 004

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Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #List of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircompDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function Description3 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleSram Interface Uart InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsDevice Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorPower Interface Sheet 1 PowerName Nominal Description Voltage De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-CouplingHDD HDD General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAMII Signal Considerations Smii Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD @33 MHz Electrical InterfaceTopology @66 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesIntroduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitrySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock GroupParameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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