Intel IXP45X, IXP46X manual Revision History, Date Revision Description

Page 7

Revision History—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Revision History

	Date	Revision	Description

			• Section 1.4, Figure 1, Figure 2, Section 3.5: Updated the number
			of supported SMII ports from six to three.
			• Table 11, Table 12, Table 16: Updated pin type for
			UTP_OP_ADDR[4:0], UTP_IP_ADDR[4:0], and ETH_MDC.
	February 2007	004	• Section 7.0, “DDR-SDRAM” : Updated design information.
	February 2007	004	• Removed SS-SMII references since this feature is not supported.

			• Incorporated specification changes, specification clarifications and
			document changes from the Intel® IXP4XX Product Line of
			Network Processors Specification Update (306428-006)
			• Updated Intel® product branding.
			The following changes were made in this release:
			• Table 4: added ECC signal interface recommendation.
			• Table 5: corrected EX_IOWAIT_N and EX_WAIT_N pull-up
			recommendations.
			• Section 3.3.2, Table 5, Section 3.3.3, Section 3.3.4, and
			Section 3.3.6: changed pull-down resistor value from 10K to 4.7K.
			• Table 16: corrected UTP_OP_SOC pull-down recommendation.
	August 2005	003	• Section 3.12.2: clarified description.
	August 2005	003	• Added new information: Section 3.12.3, “Supporting 5 V PCI

			Interface” and Section 3.12.4, “PCI Option Interface” .
			• Section 3.12.5: clarified 5V support.
			• Table 24: updated power supply requirements for 667 MHz core
			speed processor.
			• Section 6.2 and Section 6.3: enhanced description, figure, and
			tables.
			• Section 7.1.7.1: enhanced clock group routing guidelines.

			Updated to add support for Intel® IXP455 Network Processor.
	May 2005	002	Section 3.2.1: enhanced signal descriptions for DDRI_CK[2:0] and
			DDRI_CB[7:0].

	March 2005	001	Initial release of document.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261, Revision: 004	7

Image 7

Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationList of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram InterfaceDdrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircveninnDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 13 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceSram Interface Uart InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2Device Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockPower Interface Sheet 1 PowerName Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance RecommendationsHDD HDD Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations Smii Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD @66 MHz Electrical InterfaceTopology @33 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingDDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals IntroductionDDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompDDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter DefinitionTransmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock GroupDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108