Intel IXP45X, IXP46X manual Jtag Interface, PCI Host/Option Interface Pin Description Sheet 3

Page 53

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Table 21.

PCI Host/Option Interface Pin Description (Sheet 3 of 3)

 

 

 

 

 

 

 

 

Host

 

Option

 

Name

 

Input

Device-Pin Connection

Input

Description

 

Outpu

Outpu

 

 

 

 

 

 

t

 

t

 

 

 

 

 

 

 

 

 

 

Connect PCI_INTA_N output from the

 

Interrupt A

PCI_INTA_N

 

O/D

Option to one of the GPIO input signals

 

This interrupt is generated from the Option to

 

of the Host. The GPIO signal at the

O/D

one of the GPIO inputs to the Host.

 

 

 

Host must be configure as an input

 

On the Host this signal is not used, it should

 

 

 

interrupt level sensitive.

 

be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

Clock must be connected to both

 

 

PCI_CLKIN

 

I

devices. Trace lengths must be

I

Clock input

 

matched. Use point to point clock

 

 

 

 

 

 

 

 

distribution.

 

 

 

 

 

 

 

 

3.12.5Design Notes

•The IXP45X/IXP46X network processors do not support the 5 V PCI signal interface by itself. Only the 3.3 V signal interface is supported without signal level conversion, however, it is possible to interface to 5 V logic when using a voltage level converter. See Figure 17 for details.

•The PCI Local Bus Specification, Rev. 2.2 requires that the bus is always “parked”, as some device is always driving the AD lines. There is need to use pull-ups on these signals. The specification states that the following control lines should be pulled up:

— FRAME#

— TRDY#

— IRDY#

— DEVSEL#

— STOP#

— SERR#

— PERR#

— LOCK#

— INTA#

— INTB#

— INTC#

— INTD#

•The processors’ GPIO pins can be used by PCI devices on PCI slots to request an interrupt from the processors’ PCI controller.

•PCI_INTA_N is used to request interrupts to external PCI Masters. This signal is an open collector and requires a pull-up resistor.

3.13JTAG Interface

JTAG is the popular name for IEEE standards 1149.1-1990 and 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture, which provides support for:

•Board-level boundary-scan connectivity testing

•Connection to software debugging tools through the JTAG interface

•In-system programming of programmable memory and logic devices on the PCB

The interface is controlled through five dedicated test access port (TAP) pins: TDI, TMS, TCK, nTRST, and TDO, as described in the IEEE 1149.1 standard. The boundary-scan test-logic elements include the TAP pins, TAP controller, instruction register, boundary- scan register, bypass register, device identification register, and data-specific registers. These are described in the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

The IXP45X/IXP46X network processors may be controlled during debug through a JTAG interface to the processor, the debug tools such as the Macraigor* Raven*, EPI* Majic*, Wind River Systems* visionPROBE* / visionICE* or various other JTAG tools plug into the JTAG interface through a connector.

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

February 2007

HDD

Document Number: 305261; Revision: 004

53

Page 52 Page 54
Image 53
Page 52 Page 54
Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationTerm Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn DdrircompDDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Name Function Description Boot/Reset Strapping Configuration Sheet 14 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceDesign Notes Uart InterfaceSram Interface Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorName Nominal Description Voltage PowerPower Interface Sheet 1 Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsUSB Considerations Smii Signal ConsiderationsMII Signal Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD Topology Electrical Interface@33 MHz @66 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingGroup Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40DDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDdrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompData, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenSimulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
Top Page Image Contents