Intel IXP46X, IXP45X manual Smii

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Introduction

•32-bit PCI interface Master/Target 33/66 MHz

•Device Universal Serial Bus (USB) Controller

•Host Universal Serial Bus (USB) Controller

•DDRI-266 SDRAM (133-MHz Clock, 266-Mbps per data line) — User-enabled ECC, supports up to 1 Gbyte of external memory

•32-bit Expansion Bus Interface — Master/Target interface

•Two UART ports

•Up to three Ethernet ports (consult device part number for enabled features) MII/

SMII

•Up to three NPEs

•UTOPIA Level 2 Interface

•Synchronous Serial Port Interface (SSP)

•Two High-Speed Serial Port Interfaces (HSS)

•Inter-Integrated Circuit (IIC or I2C) Interface

•16 GPIO (General Purpose Input Output)

•Packaging

—544-pin PBGA package

—Commercial temperature (0° to +70° C)

—Extended temperature (-40° to +85° C)

For a complete features list and block diagram description, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet.

Note: Some features require Intel-supplied software. To determine if a feature is enabled in a particular software release, refer to the Intel® IXP400 Software Specification Update.

A block diagram of all major internal hardware components of the IXP465 network processor is given in Figure 1. The illustration also shows how the components interface with each other through the various bus interfaces such as the North AHB, South AHB, and APB.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	December 2006
12	Document Number: 305261; Revision: 004

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Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn DdrircompExpansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function DescriptionBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleUart Interface Sram InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleSignal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsMAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorPower Power Interface Sheet 1Name Nominal Description Voltage Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGASmii Signal Considerations MII Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD Electrical Interface Topology@33 MHz @66 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitryDDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Resistive Compensation Register Rcomp Clock GroupClock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108