Intel IXP46X, IXP45X manual Cross-Talk, EMI-Design Considerations

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

•Wherever possible, use a perfect symmetry within a differential pair.

•Minimize the number vias.

•Avoid routing other signals close by or in parallel to the differential pair, maintaining no less than 50 mil to any other signal.

•Maintain control impedance for each differential pair to 90 Ω +/- 15 Ω.

•Use high value ferrite beads (100 MHz/60 Ω – 100 MHz/240 Ω).

5.2.6Cross-Talk

Cross-talk is caused by capacitance and inductance coupling between signals. It is composed of both backward and forward cross-talk components.

Backward cross-talk creates an induced signal on the network that propagates in the opposite direction of the aggressor signal. Forward cross-talk creates a signal that propagates in the same direction as the aggressor signal.

Circuit board analysis software should be used to analyze your board layout for cross- talk problems.

•To effectively route signals on the PCB, signals are grouped (address, data, etc.).

—The space between groups can be 3 w (where w is the width of the traces).

—Space within a group can be just 1 w.

—Space between clock signals or clock to any other signal should be 3 w. The coupled noise between adjacent traces decreases by the square of the distance between the adjacent traces.

5.2.7EMI-Design Considerations

It is strongly recommended that good electromagnetic interference (EMI) design practices be followed when designing with the IXP45X/IXP46X network processors.

•Information on spread-spectrum clocking is available in Intel® IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor: Spread-Spectrum Clocking to Reduce EMI Application Note.

•Place high-current devices as closely as possible to the power sources.

•Proper termination of signals can reduce reflections, which may emit a high- frequency component that may contribute to more EMI than the original signal itself.

•Ferrite beads may be used to add high frequency loss to a circuit without introducing power loss at DC and low frequencies. They are effective when used to absorb high-frequency oscillations from switching transients or parasitic resonances within a circuit.

•Keep rise and fall times as slow as possible. Signals with fast rise and fall times contain many high-frequency harmonics which may radiate significantly.

•A solid ground is essential at the I/O connector to chassis and ground plane.

•Keep the power plane shorter than the ground plane by at least 5x the spacing between the power and ground planes.

•Stitch together all ground planes around the edge to the board every 100 to 200 mil. This helps reduce EMI radiating out of the board from inner layers.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

 

HDD

February 2007

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Document Number: 305261; Revision: 004

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Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn DdrircompDDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Boot/Reset Strapping Configuration Sheet 1 Name Function Description4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleDesign Notes Uart InterfaceSram Interface Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleMII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsNPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorName Nominal Description Voltage PowerPower Interface Sheet 1 Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAUSB Considerations Smii Signal ConsiderationsMII Signal Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD Electrical Interface Topology@33 MHz @66 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitryDdrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock GroupClock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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