Intel IXP46X, IXP45X manual Control Group Topology Transmission Line Characteristics

Page 98

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

7.2.3Control Group

The control signal group includes the signals DDRI_CS[1:0] and DDRI_CKE[1:0]. The following simulations were constructed for the 2 bank x16 device configuration where each signal would have three receivers.

Table 38 identifies the transmission line lengths for the chip select (CS0) topology shown in Figure 43 on page 98. These lengths were chosen as realistic goals given the IXP45X/IXP46X network processors to DDR body to body separation of no more than 500 mils.

Table 38. Control Group Topology Transmission Line Characteristics

Transmission Line	Length

TL1 (Tpd = 175 ps/in)	~ 600 mils
TL2 (Tpd = 175 ps/in)	~ 50 mils
TL3 (Tpd = 175 ps/in)	~ 1,100 mils
TL4 (Tpd = 175 ps/in)	~ 50 mils
TL5, TL6, TL7 (Tpd = 175 ps/in)	~ 800 mils
TL8, TL9, TL10 (Tpd = 175 ps/in)	~ 300 mils

Figure 43. DDR Control (CS0) Topology: Two-Bank x16 Devices

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
98	Document Number: 305261, Revision: 004

Image 98

Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircompDDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Boot/Reset Strapping Configuration Sheet 1 Name Function Description4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleDesign Notes Uart InterfaceSram Interface Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleMII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsNPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorName Nominal Description Voltage PowerPower Interface Sheet 1 De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-CouplingHDD HDD General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAUSB Considerations Smii Signal ConsiderationsMII Signal Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD @33 MHz Electrical InterfaceTopology @66 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesIntroduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitryDdrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock GroupParameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108