Intel IXP46X, IXP45X manual 104

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

Figure 48. DDR RAS Simulation Results: Two-Bank x16 Devices

The simulation results in Figure 48 are for the RAS circuit, the voltage waveform meets the DDR device input voltage requirements. Vil(max) of Vref – 0.310 or 940 mV and Vih(min) of Vref + 0.310 or 1.56 V are easily achieved at the receiver (DDR_DEVICE1). The receiver waveform must also not exceed a maximum voltage of Vin(max) = 2.8 V or the minimum voltage of Vin(min) = -0.3 V.

Waveform results for devices DDR_DEVICE2 through DDR_DEVICE6 are not shown as they are identical to that of device DDR_DEVICE1 due to symmetry. When final routing data is available, simulation results for all receivers are analyzed as variations in routing may result in differences. These differences should be minimal.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
104	Document Number: 305261, Revision: 004

Image 104

Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn DdrircompDDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Boot/Reset Strapping Configuration Sheet 1 Name Function Description4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleDesign Notes Uart InterfaceSram Interface Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleMII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsNPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorName Nominal Description Voltage PowerPower Interface Sheet 1 Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAUSB Considerations Smii Signal ConsiderationsMII Signal Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD Electrical Interface Topology@33 MHz @66 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitryDdrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock GroupClock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108