Intel IXP45X, IXP46X manual General Layout and Routing Guide, General Layout Guidelines

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General Layout and Routing Guide—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

5.0General Layout and Routing Guide

5.1Overview

This chapter provides routing and layout guides for hardware and systems based on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors.

The high-speed clocking required when designing with the processors requires special attention to signal integrity. In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid designers with board layout. In cases where it is too difficult to follow a design rule, engineering judgment must be used.

5.2General Layout Guidelines

The layout guidelines recommended in this section are based on experience and knowledge gained from previous designs. Layer stacking varies, depending on design complexity, however following standard rules helps minimize potential problems dealing with signal integrity.

The following are well know documented recommendations that helps route a functional board:

•Providing enough routing layers to comply with minimum and maximum timing requirements of the IXP45X/IXP46X network processors and other components.

•Connectors, and mounting holes must be placed in a ways that will not interfere with basic design guidelines in this document.

•Provide uniform impedance throughout the board, specially for high speed areas such us clocking, DDR-SDRAM, PCI, device bus, etc.

•Place analog, high-voltage, power supply, low-speed, and high-speed devices in different sections of the board.

•Decoupling capacitors must be placed next to power pins.

•Series termination resistors must be placed close to the source.

•Analog and digital sections of the board must be physically isolated from each other. No common ground, power planes, and signal traces are allowed to cross- isolation zones. Use appropriately sized PCB traces for larger enough to handle peak current. Keep away from high-speed digital signals.

•Keep stubs as short as possible (preferably, the electrical length of the stub less than half of the length of the rise time of signal).

•All critical signals should be routed before all other non-critical signals.

•Do not route signals close to the edge of the board, power or ground planes. Route signal at least 50 to 100 mils away from the edge of the plane.

•Try to match buses to the same trace length and keep them in groups adjacent to each other, away from other signals.

•Route processor address, data and control signals using a “daisy-chain” topology.

•Minimize number of vias and corners on all high speed signals.

•Do not route under crystals or clock oscillators, clock synthesizers, or magnetic devices (ferrites, toroids).

•Maintain trace spacing consistent between differential pairs and match trace length.

•Keep differential signals away from long and parallel, high-speed paths, such as clock signals and data strobe signals.

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

February 2007

HDD

Document Number: 305261; Revision: 004

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationOverview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram InterfaceDdrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircveninnExpansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceUart Interface Sram InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockPower Power Interface Sheet 1Name Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance RecommendationsHDD HDD Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsSmii Signal Considerations MII Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD @66 MHz Electrical InterfaceTopology @33 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingDDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals IntroductionDDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Clock Group Resistive Compensation Register RcompDDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter DefinitionTransmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock GroupDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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