Intel IXP45X, IXP46X manual USB Host/Device Signal Recommendations

Page 39

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

3.8.1Signal Interface

Table 15.

USB Host/Device Signal Recommendations

 

 

 

 

 

 

 

 

 

Input/

Pull

 

 

Name

 

Up/

Recommendations

 

 

Output

 

 

 

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Positive signal of the differential USB receiver/driver for the USB device interface.

USB_DPOS

 

I/O

Yes

Use an 18Ω series termination resistor at the source.

 

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

 

 

 

 

 

interface/signal should be pulled low with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Negative signal of the differential USB receiver/driver for the USB device interface.

USB_DNEG

 

I/O

Yes

Use an 18Ω series termination resistor at the source.

 

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

 

 

 

 

 

interface/signal should be pulled low with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Positive signal of the differential USB receiver/driver for the USB host interface.

USB_HPOS

 

I/O

Yes

Use a 20Ω series termination resistor at the source.

 

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

 

 

 

 

 

interface/signal should be pulled low with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Negative signal of the differential USB receiver/driver for the USB host interface.

USB_HNEG

 

I/O

Yes

Use a 20Ω series termination resistor at the source.

 

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

 

 

 

 

 

interface/signal should be pulled low with a 10-KΩresistor.

 

 

 

 

 

USB_HPEN

 

O

No

Enable to the external VBUS power source

 

 

 

 

 

 

 

 

 

 

 

External VBUS power.

USB_HPWR

 

I

Yes

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

Notes:

 

 

 

 

1.

Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

 

being disabled without asserting a system reset.

2.

Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

 

unconnected.

 

 

3.

Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only required

 

pull-ups or pull-downs in the clock-input signals.

 

 

 

 

 

 

A typical implementation of a USB interface Host down-stream is shown in Figure 11. The Host controller can not be used as a Device controller; however there is a second USB module with a Device controller capability that can be implementation for this application as shown in Figure 12. Note that depending on the data rate required, Low- speed or Full-speed, the 1.5K resistor shown near the device interface must be connected, either on the D+ or D-.

Speed configuration at the Device can be set as stated in note 1 and 2 bellow. For more details, refer to the Universal Serial Bus Specification, Revision 1.1.

Note:

1.If a 1.5-KΩ,pull-up resistor is connected to USB_DPOS line, the USB port is identified as Full-speed (12 Mbps).

2.If a 1.5-KΩ,pull-up resistor is connected to USB_DNEG line, the USB port is identified as Low-speed (1.5 Mbps).

3.The processors’ USB drivers are CMOS. They require series termination resistors on both signals of the differential pair USB_DPOS and USB_DNEG. The value of the series resistor depends upon the variation of the driver’s impedance.

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

February 2007

HDD

Document Number: 305261; Revision: 004

39

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationOverview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram InterfaceDdrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircveninnExpansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceUart Interface Sram InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockPower Power Interface Sheet 1Name Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance RecommendationsHDD HDD Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsSmii Signal Considerations MII Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD @66 MHz Electrical InterfaceTopology @33 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingDDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals IntroductionDDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Clock Group Resistive Compensation Register RcompDDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter DefinitionTransmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock GroupDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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