Intel IXP45X, IXP46X manual Controlled-impedance traces Low-impedance power distribution

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General PCB Guide—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

•Poor routing density

•Uncontrolled signal trace impedance

•Lack of power/ground planes, resulting in unacceptable cross-talk

•Relatively high-impedance power distribution circuitry, resulting in noise on the power and ground rails

•High-speed circuits require multi-layer printed circuit boards:

—Advantages:

•Controlled-impedance traces

•Low-impedance power distribution

—Disadvantages:

•Higher cost

•More weight

•Manufactured by fewer vendors

•Symmetry is essential to keep the board stack-up symmetric about the center This minimizes warping

•For best impedance control, have:

—No more than two signal layers between every power/ground plane pair

—No more than one embedded micro-strip layer under the top/bottom layers

•For best noise control, route adjacent layers orthogonally. Avoid layer-to-layer parallelism.

•Fabrication house must agree on design rules, including:

—Trace width, trace separation

—Drill/via sizes

•The distance between the signal layer and ground (or power) should be minimized to reduce the loop area enclosed by the return current

—Use 0.7:1 ratio as a minimum.

For example: 5-mil traces, 7-mil prepreg thickness to adjacent power/ground.

Figure 20 gives an example for a six-layer and eight-layer board. For stripline (signals between planes), the stackup should be such that the signal line is closer to one of the planes by a factor of five or more. Then the trace impedance is controlled predominantly by the distance to the nearest plane.

Figure 20 and Figure 21 illustrate the proposed stackup for the six- and eight-layer boards.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	61

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationList of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn DdrircompDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 13 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceSram Interface Uart InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2Device Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorPower Interface Sheet 1 PowerName Nominal Description Voltage Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations Smii Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD Topology Electrical Interface@33 MHz @66 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingGroup Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40DDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompData, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenSimulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108