Intel IXP46X, IXP45X manual DDR Sdram

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

Figure 28. Processor-DDR Interface

	DDRI_DQ[31:0]	DATA[31:0]	DQ[31:0]
Processors	DDRI_MA[13:0]	ADDRESS[13:0]	A[13:0]
	DDRI_CK[2:0]	CLOCK[2:0], CLOCK#[2:0]	CK[2:0]
	DDRI_CK_N[2:0]		CK#[2:0]
	DDRI_CKE[1:0]	CLOCK ENABLE[1:0]	CKE[1:0]
Line of Network
	DDRI_CS_N[1:0]	CHIP SELECT#[1:0]	CS#[1:0]	DDR SDRAM
	DDRI_BA[1:0]	BANK SELECT[1:0]	BA[1:0]
®Product	DDRI_CB[7:0]	ECC DATA[7:0]	DQ[7:0]
	DDRI_DM[4:0]	DATA MASK[4:0]	DM[4:0]
Intel	DDRI_DQS[4:0]	DATA STROBE[4:0]	DQS[4:0]
	DDRI_WE_N		WE#
	DDRI_RAS_N	WRITE#, RAS#, CAS#	RAS#
	DDRI_CAS_N		CAS#
				B3986-001

Table 28 provides a list of supported memory configurations that can be implemented for one or two banks. Notice that depending on the number of devices used, loading of the driving signals is affected. The most critical signal affected by the loading is the DDRI_CK (clock output). This signal has a very strict timing requirement defined in the JEDEC standard, therefore signal integrity of this signal is a must. The following table shows how to assign the number of devices per clock line for the various configuration. It also suggest to use a DDR SSTL zero delay clock driver when more than two devices per clock line are connected. From Table 28, any time the word “driver” appears, it is meant to let designers know that for that particular configuration, a clock driver is required. One recommended clock driver can be the Pericom PI6CV855 or a similar device. The Pericom device is highly used in DIMM memory modules that required to deliver clocks to many devices in a single module.

The best approach is to minimize the number of devices used to get the target total memory size required by design.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
76	Document Number: 305261, Revision: 004