Intel IXP45X manual DDR Command and Control Setup and Hold Values, Symbol Parameter Min Max Units

DDR-SDRAM—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

7.1.2Signal-Timing Analysis

Figure 31. DDR Command and Control Setup and Hold

T1	T2
T3	T4
T5	T6
DDR_M_CLK
Control/Command Valid
	B3988-001

Table 29. DDR Command and Control Setup and Hold Values

Symbol		Parameter	Min	Max	Units	Notes
		Output of IXP45X/IXP46X network processors valid for
T1		Command and Control signals prior to the transition of	1.5		ns	1
		DDR_M_CLK
T2		Output hold time of IXP45X/IXP46X network processors for
		Command and Control signals after the transition of	1.5		ns	1
		DDR_M_CLK
T3		Required Command and Control input setup time at DDR	0.9		ns	1
		memory device
T4		Required Command and Control input hold time at DDR	0.9		ns	1
		memory device
		Allowable setup time difference between IXP45X/IXP46X
T5		network processors Command and Control output and setup		0.6	ns	1
		time required by DDR memory device
T6		Allowable hold time difference between IXP45X/IXP46X
		network processors Command and Control output and hold		0.6	ns	1
		time required by DDR memory device
Notes:
1.	DDR_M_CLK represents the combined clock signal for DDRI_CK and DDRI_CK_N.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261, Revision: 004	81