Intel IXP45X, IXP46X manual 3 8-Bit Device Interface, 4 16-Bit Device Interface

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General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Table 6.

Boot/Reset Strapping Configuration (Sheet 2 of 2)

 

 

 

 

 

 

Name

Function

 

Description

 

 

 

 

 

 

 

Enables the PCI Controller Arbiter

 

EX_ADDR[2]

PCI_ARB

0

= PCI arbiter disabled

 

 

 

1

= PCI arbiter enabled

 

 

 

 

 

 

 

Configures the PCI Controller as PCI Bus Host

 

EX_ADDR[1]

PCI_HOST

0

= PCI as non-host

 

 

 

1

= PCI as host

 

 

 

 

 

 

 

Specifies the data bus width of the FLASH memory device found on Chip Select 0.

 

 

 

The data bus is based upon bits 0 and 7 of Configuration Register 0.

 

 

 

32_FLASH 8/16_FLASH Data bus size

 

 

 

 

B7 . B0

 

EX_ADDR[0]

8/16_FLASH

-------------------------------------------------------------------------------------

0. . 0 16-bit

0. . 1 8-bit

1. . 0 (Reserved)

1. . 1 32-bit

3.3.38-Bit Device Interface

The IXP45X/IXP46X network processors support 8-bit-wide data bus devices (byte mode). For Intel interface cycles, the data lines and control signals can be connected as shown in Figure 3 on page 25 and Figure 4 on page 26. During byte mode accesses, the remaining data signals not being used EX_DATA[31:8], are driven by the processor to an unpredictable state on WRITE cycles and tri-stated during READ cycles.

When booting an 8-bit flash device, the expansion bus must be configured during reset to the 8-bit mode (see Configuration Register 0). To accomplish this, boot-strapping is required in certain address pins of the Expansion bus. For example, as in this case when booting of an 8-bit flash device, bit 0 and 7 of Configuration Register 0 must be set as follows:

Bit 0 = 1. By default this bit is set high when coming off reset or any time reset is asserted.

Bit 7 = 0. This can be done by placing an external 4.7-KΩpull-down resistor to pin EX_ADDR[7].

If it is required to change access mode, after the system has booted, and during normal operation; the Timing and Control Register for Chip Select must be configured to perform the desired mode access. For a complete description on accomplishing this refer to the “Expansion Bus” chapter in the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

3.3.416-Bit Device Interface

The IXP45X/IXP46X network processors support 16-bit wide data bus devices (16-bit word mode). For Intel interface cycles, the data lines and control signals can be connected as shown in Figure 3 on page 25 and Figure 4 on page 26. During word mode accesses, the remaining data signals not being used EX_DATA[31:16], are driven by the processor to an unpredictable state on WRITE cycles and tri-stated during READ cycles.

When booting a 16-bit flash device, the expansion bus must be configured during reset to the 16-bit mode (see Configuration Register 0). To accomplish this, boot-strapping is required in certain address pins of the Expansion bus.

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

February 2007

HDD

Document Number: 305261; Revision: 004

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationTerm Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram InterfaceDdrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircveninnDDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Name Function Description Boot/Reset Strapping Configuration Sheet 14 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceDesign Notes Uart InterfaceSram Interface Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockName Nominal Description Voltage PowerPower Interface Sheet 1 VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance RecommendationsHDD HDD Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsUSB Considerations Smii Signal ConsiderationsMII Signal Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD @66 MHz Electrical InterfaceTopology @33 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingDDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals IntroductionDDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDdrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompDDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter DefinitionTransmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock GroupDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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