Intel IXP45X, IXP46X manual Figures

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Contents—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

	7.1.7.1 Clock Group	88
	7.1.7.2 Data, Command, and Control Groups	89
7.2 Simulation Results		90
7.2.1	Clock Group	90
7.2.2	Data Group	92
7.2.3	Control Group	98
7.2.4	Command Group	100
7.2.5	RCVENIN and RCVENOUT	105

Figures

1	Intel® IXP465 Component Block Diagram	13
2	Intel® IXP465 Example System Block Diagram	16
3	8/16/32-Bit Device Interface: No Byte-Enable	25
4	8/16/32-Bit Device Interface: Byte Enable	26
5	Flash Interface Example	27
6	Expansion Bus SRAM Interface	28
7	UART Interface Example	30
8	MII Interface Example	33
9	SMII Interface Example	35
10	I2C EEPROM Interface Example	38
11	USB Host Down Stream Interface Example	40
12	USB Device Interface Example	41
13	UTOPIA Interface Example	43
14	HSS Interface Example	46
15	Serial Flash and SSP Port (SPI) Interface Example	47
16	PCI Interface	50
17	PCI 3.3 V to 5 V Logic Translation Interface	51
18	Clock Oscillator Interface Example	55
19	Component Placement on a PCB	60
20	8-Layer Stackup	62
21	6-Layer Stackup	62
22	Signal Changing Reference Planes	64
23	Good Design Practice for VIA Hole Placement	65
24	Poor Design Practice for VIA Placement	65
25	Pad-to-Pad Clearance of Passive Components to a PGA or BGA	66
26	PCI Address/Data Topology	72
27	PCI Clock Topology	73
28	Processor-DDR Interface	76
29	Processor-DDR Interface: x16 Devices with ECC	79
30	VTT Terminating Circuitry	80
31	DDR Command and Control Setup and Hold	81
32	DDR Data to DQS Read Timing Parameters	82
33	DDR-Data-to-DQS-Write Timing Parameters	83
34	DDR-Clock-to-DQS-Write Timing Parameters	83
35	Printed Circuit Board Layer Stackup	85
36	Printed Circuit Board Controlled Impedance	86
37	DDR Clock Topology: Two-Bank x16 Devices	91
38	DDR Clock Simulation Results: Two-Bank x16 Devices	92
39	DDR Data Topology: Two-Bank x16 Devices	94
40	DDR Data Write Simulation Results: Two-Bank x16 Devices	95
41	DDR Data Read Simulation Results: Two-Bank x16 Devices
	(Reduced Drive Strength)	96
42	DDR Data Read Simulation Results: Two-Bank x16 Devices (Full Drive Strength)	97
43	DDR Control (CS0) Topology: Two-Bank x16 Devices	98
	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007		HDD
Document Number: 305261, Revision: 004		5

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationTerm Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn DdrircompDDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Name Function Description Boot/Reset Strapping Configuration Sheet 14 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceDesign Notes Uart InterfaceSram Interface Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorName Nominal Description Voltage PowerPower Interface Sheet 1 Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsUSB Considerations Smii Signal ConsiderationsMII Signal Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD Topology Electrical Interface@33 MHz @66 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingGroup Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40DDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDdrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompData, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenSimulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108