Intel IXP45X, IXP46X manual Reset Configuration Straps, Expansion Bus Signal Recommendations

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General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

3.3.1Signal Interface

Table 5.

Expansion Bus Signal Recommendations

 

 

 

 

 

 

 

Input

Pull

 

Name

 

Up

Recommendations

 

Output

 

 

Down

 

 

 

 

 

 

EX_CLK

 

I

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

EX_ALE

 

TRI O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

 

 

 

 

Use 4.7-KΩresistors for pull-downs; required for boot strapping for initial configuration of

 

 

 

 

Configuration Register 0. Pull-ups are not required as for when the system comes out of

EX_ADDR[24:0]

 

I/O

Yes

reset, all bits are initially set HIGH. For more details, see Table 6.

 

 

 

 

For additional details on address strapping, see the Intel® IXP45X and Intel® IXP46X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

EX_WR_N

 

I/O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

EX_RD_N

 

I/O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

EX_CS_N[7:0]

 

I/O

Yes

Use series termination resistor, 10Ω to 33Ω at the source.

 

Use 10KΩ resistors pull-ups to ensure that the signal remains de-asserted.

 

 

 

 

 

 

 

 

 

EX_DATA[31:0]

 

I/O

No

 

 

 

 

 

 

EX_BE_N[3:0]

 

I/O

No

 

 

 

 

 

 

EX_IOWAIT_N

 

I

Yes

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

EX_RDY_N[3:0]

 

I

Yes

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

EX_PARITY[3:0]

 

I/O

No

 

 

 

 

 

 

EX_REQ_N[3:1]

 

I

Yes

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

EX_REQ_GNT_N

 

I

Yes

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

EX_GNT_N[3:1]

 

O

No

 

 

 

 

 

 

EX_GNT_REQ_N

 

O

No

 

 

 

 

 

 

EX_SLAVE_CS_N

 

I

Yes

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

EX_BURST

 

I

Yes

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

EX_WAIT_N

 

TRI O

No

 

 

 

 

 

 

3.3.2Reset Configuration Straps

At power up or whenever RESET_IN_N is asserted, the Expansion-bus address outputs are switched to inputs and the state of the inputs are captured and stored in Configuration Register 0, bits 24 through 0. This occurs when PLL_LOCKED is de- asserted.

The strapping of Expansion-bus address pins can be done by placing external pull-down resistors at the required address pin. It is not required to use external pull-up resistors, by default upon reset all bits on Configuration Register 0 are set High, unless an external pull down is used to set them Low. For example to register a bit low or high in the Configuration Register 0, do the following:

Place an external 4.7-KΩpull-down resistor to set a bit LOW.

No external pull-up is required, by default upon reset, bits are set HIGH.

The state of the boot-strapping resistor is register on the first cycle after the synchronous de-assertion of the reset signal. These bits can be read or written as needed for desired configurations. It is recommended that only Bit 31, Memory Map, be changed from 1 to 0 after execution of boot code from external flash.

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

February 2007

HDD

Document Number: 305261; Revision: 004

21

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationOverview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn DdrircompExpansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceUart Interface Sram InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorPower Power Interface Sheet 1Name Nominal Description Voltage Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsSmii Signal Considerations MII Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD Topology Electrical Interface@33 MHz @66 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingGroup Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40DDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Clock Group Resistive Compensation Register RcompData, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenSimulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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