Intel IXP45X, IXP46X manual HSS Interface, Utopia Interface Example

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General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 13. UTOPIA Interface Example

Intel® IXP45X/46X
Product Line
Network Processor	Control Signals
EX_BUS	Control Signals
EX_BUS
			Analog Front
ATM Layer Device	25 MHz	ADSL Framer	End
		Multi-Channel	AFE	RJ11
UTP_OP_CLK		TXCLK
UTP_OP_FCO		TXENB#
UTP_OP_ADDR[4:0]		TXADDR[4:0]
UTP_OP_FCI		TXCLAV
UTP_OP_SOC		TXSOC
UTP_OP_DATA[7:0]		TXDATA[7:0]
UTP_IP_FCO		RXENB#
UTP_IP_ADDR[4:0]		RXADDR[4:0]
UTP_IP_FCI		RXCLAV
UTP_IP_SOC		RXSOC
UTP_IP_DATA[7:0]		RXDATA[7:0]	AFE	RJ11
UTP_IP_CLK		RXCLK	AFE	RJ11
UTP_IP_CLK		RXCLK
UTOPIA Level 2
Interface	25 MHz
	25 MHz	SDRAM
		SDRAM
		Local Memory
				B4107 -003

3.10HSS Interface

NPE A has an integrated High-Speed Serial (HSS) module, whose primary function is to provide connectivity between the internal NPE A and the external HSS interface. There are two HSS ports that can directly interface to SLIC/CODEC devices for voice applications, or serial DSL framers. The HSS ports are software configurable to support various serial protocols, such as T1/ E1/J1, and MVIP. For a list of supported protocols, see the Intel® IXP400 Software Programmer’s Guide.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	43

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationList of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram InterfaceDdrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircveninnDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 13 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceSram Interface Uart InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2Device Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockPower Interface Sheet 1 PowerName Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance RecommendationsHDD HDD Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations Smii Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD @66 MHz Electrical InterfaceTopology @33 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingDDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals IntroductionDDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompDDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter DefinitionTransmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock GroupDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108