Intel IXP45X, IXP46X manual PCI Option Interface, PCI Host/Option Interface Pin Description Sheet 1

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General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 17. PCI 3.3 V to 5 V Logic Translation Interface

Intel® IXP46X	3.3V LOGIC		3.3V Logic
Product Line	3.3V LOGIC	PCI Device_ 1
Product Line		PCI Device_ 1
Network Processor
	3.3V LOGIC		3.3V Logic
	3.3V LOGIC	PCI Device_2
		PCI Device_2
	3.3V LOGIC		3.3V Logic
	3.3V LOGIC	PCI Device_3
	32-Bit BUS	PCI Device_3
	32-Bit BUS
				5.0V
	1K	74CBT3384A
		OE	VCC	4.3V
PCI		10-BIT
Interface			GND	5.0V LOGIC	5.0V Logic
Interface	3.3V LOGIC				5.0V Logic
	3.3V LOGIC		VCC		PCI Device_4
			VCC
	1K	10-BIT		2.87K
	1K
		OE	GND
		74CBT3384A
					B5197 -01

3.12.4PCI Option Interface

The IXP45X/IXP46X network processors can be used in a design as a host or as an option device. This section describes how the IXP45X/IXP46X network processors can be connected as an option device to obtain proper functionality. There are slight differences in the hardware interface when designing for option mode. All routing and board recommendations described in previous sections of this document apply, however the design must use the device pin connections listed in Table 21.

Table 21. PCI Host/Option Interface Pin Description (Sheet 1 of 3)

		Host		Option
	Name	Input	Device-Pin Connection	Input	Description
	Name	Outpu	Device-Pin Connection	Outpu	Description
		Outpu		Outpu
		t		t

	PCI_AD[31:0]	I/O	All address/data signals need to be	I/O	PCI Address/Data bus
	PCI_AD[31:0]	I/O	connected between the two devices.	I/O	PCI Address/Data bus
			connected between the two devices.

	PCI_CBE_N[3:0]	I/O	Connect signals to same pins between	I/O	PCI Command/Byte Enables
	PCI_CBE_N[3:0]	I/O	the two devices.	I/O	PCI Command/Byte Enables
			the two devices.

	PCI_PAR	I/O	Connect signal to same pin between	I/O	PCI Parity
	PCI_PAR	I/O	the two devices.	I/O	PCI Parity
			the two devices.

			Connect signal to same pin between
	PCI_FRAME_N	I/O	the two devices.	I/O	PCI Cycle Frame
			Connect a 10-KΩpull-up resistor.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	51

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Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationOverview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram InterfaceDdrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircveninnExpansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceUart Interface Sram InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockPower Power Interface Sheet 1Name Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance RecommendationsHDD HDD Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsSmii Signal Considerations MII Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD @66 MHz Electrical InterfaceTopology @33 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingDDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals IntroductionDDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Clock Group Resistive Compensation Register RcompDDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter DefinitionTransmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock GroupDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108