Intel IXP45X, IXP46X manual PCI Interface Block Diagram, PCI Controller Sheet 2

Page 49

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Table 20.

PCI Controller (Sheet 2 of 2)

 

 

 

 

 

 

 

 

 

Input/

Pull

 

 

Name

 

Outpu

Up/

Recommendations

 

 

 

t

Down

 

 

 

 

 

 

 

 

 

 

 

 

Initialization Device Select.

PCI_IDSEL

 

I

Yes

When this interface/signal is enabled and is not being used in a system design, the interface/

 

 

 

 

 

signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Arbitration Request.

PCI_REQ_N[3:1]

 

I

Yes

When this interface/signal is enabled and is not being used in a system design, the interface/

 

 

 

 

 

signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Arbitration Request:

PCI_REQ_N[0]

 

I/O

Yes

When this interface/signal is enabled and is not being used in a system design, the interface/

 

 

 

 

 

signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

PCI_GNT_N[3:1]

 

O

No

Arbitration Grant.

 

 

 

 

 

 

 

 

 

 

 

Arbitration Grant.

PCI_GNT_N[0]

 

I/O

Yes

When this interface/signal is enabled and is not being used in a system design, the interface/

 

 

 

 

 

signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Interrupt A.

PCI_INTA_N

 

O/D

Yes

When this interface/signal is enabled and is either used or not used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Clock input.

PCI_CLKIN

 

I

Yes

When this interface/signal is enabled and is not being used in a system design, the interface/

 

 

 

 

 

signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

Notes:

 

 

 

 

1.

Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

 

being disabled without asserting a system reset.

2.

Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

 

unconnected.

 

 

3.

Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require

 

pull-ups or pull-downs in the clock-input signals.

 

 

 

 

 

 

3.12.2PCI Interface Block Diagram

When using the IXP45X/IXP46X network processors in Master mode, the PCI module can interface to up to four PCI cards (devices) at 33 MHz or two PCI cards at 66 MHz. The limitation to two cards (devices) at 66 MHz is due to load requirements to maintain signal integrity at the higher frequency.

The PCI-to-PCI bridge must be used in order to address the PCI requirement not to exceed one load per PCI connector unless it is through a PCI-to-PCI bridge.

The IDSEL signals on the PCI slots can be connected to one of the PCI_AD lines, preferable to the higher order address signals. Reset support can be accomplished by using one of the GPIO pins to generate a reset or through an external decoder of the Expansion bus.

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

February 2007

HDD

Document Number: 305261; Revision: 004

49

Page 48 Page 50
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Page 48 Page 50
Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationList of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn DdrircompDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 13 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceSram Interface Uart InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2Device Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorPower Interface Sheet 1 PowerName Nominal Description Voltage Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations Smii Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD Topology Electrical Interface@33 MHz @66 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingGroup Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40DDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompData, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenSimulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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