Intel IXP45X, IXP46X manual Clock Signal Group Routing Guidelines, Parameter Definition

Page 89

DDR-SDRAM—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Table 34.

Clock Signal Group Routing Guidelines

 

 

 

 

 

 

Parameter

Definition

 

 

 

 

Signal Group Members

DDRI_CK[2:0] and DDRI_CK_N[2:0]

 

 

 

 

Topology

Differential Pair Point to Point (1 Driver, 2 Receivers)

 

 

 

 

Single Ended Trace Impedance (Zo)

60 Ωs

 

Differential Mode Impedance (Zdiff)

120 Ωs

 

Nominal Trace Width1

Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils

 

Nominal Pair Spacing (edge to edge) 2

Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils

 

Minimum Pair to Pair Spacing

Any layer 20mils

 

 

 

 

Minimum Spacing to Other DDR Signals

20.0 mils

 

 

 

 

Minimum Spacing to non-DDR Signals

25.0 mils

 

 

 

 

 

Maximum Via Count

4 per trace

 

8 per differential pair

 

 

 

 

 

 

 

DDRI_CK to DDRI_CK_N Length Matching

Match total length to +/- 10 mils between clocks

 

 

 

 

 

Notes:

 

 

 

1.

Nominal trace width is determined by board physical characteristics and stack-up. This value should

 

 

be verified with the PWB manufacturer to achieve the desired Zo.

 

2.

Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value

 

 

should be verified with the PWB manufacturer to achieve the desired Zdiff.

 

 

 

 

7.1.7.2Data, Command, and Control Groups

The data, command, and control signal groups include all signals other than the clock group signals. The groups should be routed on internal layers, except for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all signals. Surface layer routing should be minimized. The following table provides routing guidelines for signals within these groups.

Table 35. Data, Command, and Control Group Routing Guidelines

 

Parameter

Definition

 

 

 

 

 

DDRI_CB[7:0], DDRI_DQ[31:0], DDRI_DQS[4:0], DDRI_DM[4:0],

Signal Group Members

DDRI_CKE[1:0], DDRI_CS_N[1:0], DDRI_MA[13:0],

 

 

DDRI_BA[1:0], DDRI_RAS_N, DDRI_CAS_N, DDRI_WE_N

 

 

Topology

Single-Ended, Point-to-Point (1 Driver, 6 Receivers max)

 

 

Single Ended Trace Impedance (Zo)

50 Ω

Nominal Trace Width1

Layers 3, 4, 6, 7, 9, and 10: 5.7 mils

Minimum Spacing to DDR Clock Signals

20.0 mils

 

 

Minimum Spacing to other DDR Signals

10.0 mils

 

 

Minimum Spacing to non-DDR Signals

25.0 mils

 

 

Maximum Via Count

6 per signal

 

 

Length Matching

See Table 33 on page 87

 

 

 

Notes:

 

 

1.

Nominal trace width is determined by board physical characteristics and stack-up. This value should

 

be verified with the PWB manufacturer to achieve the desired Zo.

 

 

 

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

February 2007

HDD

Document Number: 305261, Revision: 004

89

Page 88 Page 90
Image 89
Page 88 Page 90
Contents February Hardware Design GuidelinesHDD Contents 12.1 Figures Tables Control Group Topology Transmission Line CharacteristicsDate Revision Description Revision HistoryHDD Chapter Name Description Content OverviewTitle Document # Related DocumentationTerm Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Dslam Typical ApplicationsSystem Memory Map System Architecture DescriptionIntel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn DdrircompDDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Name Function Description Boot/Reset Strapping Configuration Sheet 14 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash InterfaceDesign Notes Uart InterfaceSram Interface Name Input Pull Recommendations Output Down Uart Signal RecommendationsUart Interface Example MII/SMII InterfaceMII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Smii Signal Recommendations NPE A, B, C Signal Interface, SmiiDevice Connection, Smii Gpio InterfaceGpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface I2C Eeprom Interface Example USB InterfaceUSB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 InterfaceUtopia Signal Recommendations Utopia Interface Example HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPCI Interface Supporting 5 V PCI InterfacePCI Host/Option Interface Pin Description Sheet 1 PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorName Nominal Description Voltage PowerPower Interface Sheet 1 Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsUSB Considerations Smii Signal ConsiderationsMII Signal Considerations EMI-Design Considerations Cross-TalkTrace Impedance Power and Ground PlaneHDD Topology Electrical Interface@33 MHz @66 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingGroup Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40DDR Sdram HDD Clock Banks Memory Size Supported Memory ConfigurationsVTT VTT Terminating Circuitry Selecting VTT Power SupplyDdrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled ImpedancePrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register RcompData, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenSimulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data GroupData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line CharacteristicsDDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command GroupDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and RcvenoutDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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