Intel IXP46X, IXP45X Input System Clock, Clock Signals, Clock Oscillator, Name Type Description

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

3.13.1Signal Interface

	Table 22.	Synchronous Serial Peripheral Port Interface

		Input/	Pull
	Name	Input/	Up/	Recommendations
	Name	Output	Up/	Recommendations
		Output	Down

				Test mode select.
	JTG_TMS	I	Yes	Ω
				When the JTAG interface is not being used, the signal must be pulled high using a 10-k
				resistor.

				Test Input data.
	JTG_TDI	I	Yes	When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ
				resistor.

	JTG_TDO	O	O	Test Output data.

				Test Reset.
	JTG_TRST_N	I	Yes	Ω
				When the JTAG interface is not being used, the signal must be pulled low using a 10-k
				resistor.

				Test Clock.
	JTG_TCK	I	Yes	When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ
				resistor.

3.14Input System Clock

The IXP45X/IXP46X network processors require a 33.33-MHz reference clock to generate all internal clocks required — including core clock — and the various buses running internally within the system.

3.14.1Clock Signals

Table 23.	Clock Signals

	Name	Type*	Description

	OSC_IN	I	Source must be a clock input of 33.33-MHz.
	OSC_IN	I	Use a series termination resistor, 10 Ω to 33 Ω at the source.


	OSC_OUT	O	No connect

Note: For explanations of the Type column abbreviations, see Table 2 on page 17.

3.14.2Clock Oscillator

When using an external clock oscillator to supply the 33.33-MHz reference system clock, connect the clock oscillator output to OSC_IN pin through a series termination of 33 Ω as shown in Figure 18. The series termination helps smooth the rise and fall edges of the clock and eliminate ringing. Leave the OSC_OUT pin un-connected.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
54	Document Number: 305261; Revision: 004

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Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircompExpansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function DescriptionBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleUart Interface Sram InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleSignal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsMAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorPower Power Interface Sheet 1Name Nominal Description Voltage De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-CouplingHDD HDD General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGASmii Signal Considerations MII Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD @33 MHz Electrical InterfaceTopology @66 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesIntroduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitryDDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Resistive Compensation Register Rcomp Clock GroupParameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108