Intel IXP45X manual DDR Sdram Interface Pin Description Sheet 2, Ddriwen, Ddrircveninn, Ddrircomp

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Table 4.	DDR SDRAM Interface Pin Description (Sheet 2 of 2)
		Input		VTT
Name		Outpu	Device-Pin Connection	Terminatio	Description
		t		n
			The WE signal must be connected		Write Strobe — Defines whether or not the
DDRI_WE_N		O	to each device in a daisy chain	Yes	current operation by the DDR SDRAM is to be
			manner		a read or a write.
					Data Bus Mask — Controls the DDR SDRAM
			Connect to each DM device pin.		data input buffers. Asserting DDRI_WE_N
					causes the data on DDRI_DQ[31:0] and
			For the 8-bit devices connect one
					DDRI_CB[7:0] to be written into the DDR
			DM signal per device.
					SDRAM devices.
DDRI_DM[4:0]		O	For the 16-bit devices connect two	Yes
					DDRI_DM[4:0] controls this operation on a
			DM signal per device (depending
					per-byte basis. DDRI_DM[3:0] are intended to
			on how many data bits are being
					correspond to each byte of a word of data.
			used).
					DDRI_DM[4] is intended to be utilized for the
					ECC byte of data.
			The BA signals must be connected		DDR SDRAM Bank Selects — Controls which of
					the internal DDR SDRAM banks to read or
DDRI_BA[1:0]		O	to each device in a daisy chain	Yes
					write. DDRI_BA[1:0] are used for all
			manner.
					technology types supported.
			All address signals need to be		Address bits 13 through 0 — Indicates the row
DDRI_MA[13:0]		O	connected to each device in a	Yes	or column to access depending on the state of
			daisy chain manner.		DDRI_RAS_N and DDRI_CAS_N.
DDRI_DQ[31:0]		I/O	Need to be connected in parallel	Yes	Data Bus — 32-bit wide data bus.
			to achieve a 32-bit bus width.
					ECC Bus — Eight-bit error correction code
					which accompanies the data on
DDRI_CB[7:0]		I/O	Connect to ECC memory devices.	Yes	DDRI_DQ[31:0].
					When ECC is disabled and not being used in a
					system design, these signals can be left un-
					connected.
					Data Strobes Differential — Strobes that
					accompany the data to be read or written from
			Connect DQS[3:0] to devices with		the DDR SDRAM devices. Data is sampled on
					the negative and positive edges of these
DDRI_DQS[4:0]		I/O	data signals and DQS[4] to	Yes
					strobes. DDRI_DQS[3:0] are intended to
			devices with ECC signals.
					correspond to each byte of a word of data.
					DDRI_DQS4] is intended to be utilized for the
					ECC byte of data.
					Clock enables — One clock after
					DDRI_CKE[1:0] is de-asserted, data is latched
			Use one CKE per bank, never mix		on DQ[31:0] and DDRI_CB[7:0]. Burst
DDRI_CKE[1:0]		O	the CKE on the same bank. Use	Yes	counters within DDR SDRAM device are not
			CKE[0] for bank0 and CKE[1] for		incremented. De-asserting this signal places
			bank1		the DDR SDRAM in self-refresh mode. For
					normal operation, DDRI_CKE[1:0] must be
					asserted.
					RECEIVE ENABLE OUT must be connected to
			Connect RCVEOUT to RCVENIN		DDRI_RCVENIN_N signal of the IXP45X/
DDRI_RCVENOUT_N		O	and follow note on pin description	No	IXP46X product line and the propagation delay
			in this table.		of the trace length must be matched to the
					clock trace plus the average DQ Traces.
					RECEIVE ENABLE IN provides delay
					information for enabling the input receivers
DDRI_RCVENIN_N		I	Same as above	No	and must be connected to the
					DDRI_RCVENOUT_N signal of the IXP45X/
					IXP46X network processors.
DDRI_RCOMP		O	Tied off to a resistor	Tied off to a	20 Ohm Resistor connected to ground used for
				resistor	process/temperature adjustments.
					DDR SDRAM Voltage Reference — is used to
DDRI_VREF		I	VCCM/2	VCCM/2	supply the reference voltage to the differential
					inputs of the memory controller pins.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	19