Intel IXP46X, IXP45X manual PCI Host/Option Interface Pin Description Sheet 2, Pcitrdyn

Page 52

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

Table 21.

PCI Host/Option Interface Pin Description (Sheet 2 of 3)

 

 

 

 

 

 

 

 

Host

 

Option

 

Name

 

Input

Device-Pin Connection

Input

Description

 

Outpu

Outpu

 

 

 

 

 

 

t

 

t

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_TRDY_N

 

I/O

the two devices.

I/O

PCI Target Ready

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_IRDY_N

 

I/O

the two devices.

I/O

Initiator Ready

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_STOP_N

 

I/O

the two devices.

I/O

Stop

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_PERR_N

 

I/O

the two devices.

I/O

Parity Error

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_SERR_N

 

I/O

the two devices.

I/O

System Error

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_DEVSEL_N

 

I/O

the two devices.

I/O

Device Select

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect one of the higher order PCI

 

 

PCI_IDSEL

 

I

address signals to the Device.

I

Initialization Device Select

 

Connect a 10K pull-up resistor to the

 

 

 

 

 

 

 

 

Host.

 

 

 

 

 

 

 

 

 

 

 

From the Option device, connect output

 

Arbitration Request

 

 

 

 

On the Option device, these signals are not

 

 

 

signal PCI_REQ_N[0] to one of the

 

 

 

 

PCI_REQ_N[3:0] inputs to the Host.

 

used, they should be pulled high with a 10-KΩ

PCI_REQ_N[3:1]

 

I

Note: the PCI_REQ_N[n] must

I

resistor.

 

Note: The PCI_REQ_N[n] must correspond

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

to the PCI_GNT_N[n], where “n” must

 

 

 

where “n” must be the same number in

 

 

 

 

 

be the same number in the square

 

 

 

the square bracket.

 

 

 

 

 

bracket.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

From the Option device, connect output

 

Arbitration Request

 

 

 

 

On the Option device, this signal is an output

 

 

 

PCI_REQ_N[0] to one of the

 

 

 

 

PCI_REQ_N[3:0] inputs to the Host.

 

and must be connected to one of the

PCI_REQ_N[0]

 

I

Note: the PCI_REQ_N[n] must

O

PCI_REQ_N[3:0] inputs to the Host.

 

Note: The PCI_REQ_N[n] must correspond

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

to the PCI_GNT_N[n], where “n” must

 

 

 

where “n” must be the same number in

 

 

 

 

 

be the same number in the square

 

 

 

the square bracket.

 

 

 

 

 

bracket.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Connect one of the Host outputs

 

 

 

 

 

PCI_GNT_N[3:0] to PCI_GNT_N[0]

 

Arbitration Grant

 

 

 

input to the Option.

 

 

 

 

 

On the Option device, these signals are not

PCI_GNT_N[3:1]

 

O

Note: the PCI_GNT_N[n] must

O

 

used, they should be pulled high with a 10-KΩ

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

resistor.

 

 

 

where “n” must be the same number in

 

 

 

 

 

 

 

 

 

the square bracket.

 

 

 

 

 

 

 

 

 

 

 

Connect one of the Host outputs

 

Arbitration Grant

 

 

 

 

On the Option device, this signal is an input

 

 

 

PCI_GNT_N[3:0] to PCI_GNT_N[0]

 

 

 

 

input to the Option.

 

and must be connected to one of the

PCI_GNT_N[0]

 

O

Note: the PCI_GNT_N[n] must

I

PCI_GNT_N[3:0] outputs of the Host.

 

Note: The PCI_REQ_N[n] must correspond

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

to the PCI_GNT_N[n], where “n” must

 

 

 

where “n” must be the same number in

 

 

 

 

 

be the same number in the square

 

 

 

the square bracket.

 

 

 

 

 

bracket.

 

 

 

 

 

 

 

 

 

 

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

 

HDD

February 2007

52

Document Number: 305261; Revision: 004

Page 51 Page 53
Image 52
Page 51 Page 53
Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #List of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn DdrircompDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function Description3 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleSram Interface Uart InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsDevice Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorPower Interface Sheet 1 PowerName Nominal Description Voltage Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAMII Signal Considerations Smii Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD Electrical Interface Topology@33 MHz @66 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitrySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock GroupClock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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