Intel IXP46X, IXP45X manual Supported Memory Configurations, Clock Banks Memory Size

Page 78

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

Table 28.

Supported Memory Configurations

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR

Device

Number of

Devices

Number of

Devices

Number

Total

 

Device

DDR Devices

per

DDR Devices

per

 

Density

Width

(non-ECC)

Clock

(ECC)

Clock

of Banks

Memory Size

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128 Mbit

x8

4

2,2

5

2,2,1

1

64 Mbyte

 

 

 

 

 

 

 

 

 

 

128 Mbit

x8

8

Driver

10

Driver

2

128 Mbyte

 

 

 

 

 

 

 

 

 

 

128 Mbit

x16

2

1,1

3

1,1,1

1

32 Mbyte

 

 

 

 

 

 

 

 

 

 

128 Mbit

x16

4

2,2

6

2,2,2

2

64 Mbyte

 

 

 

 

 

 

 

 

 

 

256 Mbit

x8

4

2,2

5

2,2,1

1

128 Mbyte

 

 

 

 

 

 

 

 

 

 

256 Mbit

x8

8

Driver

10

Driver

2

256 Mbyte

 

 

 

 

 

 

 

 

 

 

256 Mbit

x16

2

1,1

3

1,1,1

1

64 Mbyte

 

 

 

 

 

 

 

 

 

 

256 Mbit

x16

4

2,2

6

2,2,2

2

128 Mbyte

 

 

 

 

 

 

 

 

 

 

512 Mbit

x8

4

2,2

5

2,2,1

1

256 Mbyte

 

 

 

 

 

 

 

 

 

 

512 Mbit

x8

8

Driver

10

Driver

2

512 Mbyte

 

 

 

 

 

 

 

 

 

 

512 Mbit

x16

2

1,1

3

1,1,1

1

128 Mbyte

 

 

 

 

 

 

 

 

 

 

512 Mbit

x16

4

2,2

6

2,2,2

2

256 Mbyte

 

 

 

 

 

 

 

 

 

 

1 Gbit

x8

4

2,2

5

2,2,1

1

512 Mbyte

 

 

 

 

 

 

 

 

 

 

1 Gbit

x8

8

Driver

10

Driver

2

1 Gbyte

 

 

 

 

 

 

 

 

 

 

1 Gbit

x16

2

1,1

3

1,1,1

1

256 Mbyte

 

 

 

 

 

 

 

 

 

 

1 Gbit

x16

4

2,2

6

2,2,2

2

512 Mbyte

 

 

 

 

 

 

 

 

 

Figure 29 shows the DDR memory interface of the IXP45X/IXP46X network processors using x16 devices with Error Correcting Code (ECC). Bank 0 is represented by DDR devices 1, 3, and 5. Bank 1 is represented by DDR devices 2, 4, and 6. Unused data inputs on the ECC devices (5 and 6) are pulled to ground through 10-KΩresistors.

The VTT signal termination used for all signals, except clocks, is a series 60.4-Ωresistor to a 1.25-V DC power supply designed for DDR memory termination. The appropriate value for termination resistance should be verified through simulation for the specific topology as shown in “Simulation Results” on page 90. The supply chosen for this application was the TPS54672 from Texas Instruments*.

The DDRI_RCVENOUT_N signal must be connected to the DDRI_RCVENIN_N signal with a trace which is propagation delay length matched to the average delay of the clock (DDRI_CK[2:0]) plus data (DDRI_DQ[31:0]). A series terminating resistor (Rs) should be used to control overshoot and undershoot, as shown in Figure 49 on page 105.

A resistance value in the 25- to 50-Ωrange should be used as it adds minimal propagation delay to the signal without adversely varying from the CLK plus DQ propagation delay average. The appropriate value for termination resistance should be verified through simulation for the specific topology.

The DDRI_RCOMP signal must be terminated through a 20-Ω, 1%, 0.1-W resistor (Rcomp) to ground. This allows the DDR controller to make temperature and process adjustments.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

 

HDD

February 2007

78

Document Number: 305261, Revision: 004

Page 77 Page 79
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Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircompExpansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function DescriptionBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleUart Interface Sram InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleSignal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsMAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorPower Power Interface Sheet 1Name Nominal Description Voltage De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-CouplingHDD HDD General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGASmii Signal Considerations MII Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD @33 MHz Electrical InterfaceTopology @66 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesIntroduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitryDDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Resistive Compensation Register Rcomp Clock GroupParameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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