Intel IXP46X, IXP45X manual Boot/Reset Strapping Configuration Sheet 1, Name Function Description

Page 22

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

For a complete bit description of Configuration Register 0, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

Table 6.

Boot/Reset Strapping Configuration (Sheet 1 of 2)

 

 

 

 

 

 

 

 

Name

 

Function

 

 

Description

 

 

 

 

 

 

 

EX_ADDR[24]

 

(Reserved)

(Reserved)

 

 

 

 

 

 

 

 

 

 

 

Intel XScale®

Allows changing Intel XScale® Processor clock speed. This overrides device fuse

 

EX_ADDR[23:21]

Processor

 

settings. However cannot be used to over-clock core speed.

 

 

 

Clock Set[2:0]

 

 

 

 

 

 

 

 

 

 

 

EX_ADDR[20:17]

Customer

Customer-defined bits. (Might be used for board revision.)

 

 

 

 

 

 

EX_ADDR[16:11]

(Reserved)

(Reserved)

 

 

 

 

 

 

 

 

 

 

1 = EX_IOWAIT_N is sampled during the read/write expansion bus cycles for Chip

 

 

 

 

Select 0.

 

 

 

 

 

0 = EX_IOWAIT_N is ignored for read and write cycles to Chip select 0 if

 

 

 

 

EXP_TIMING_CS0 is configured to Intel mode.

 

 

 

 

Typically, IOWAIT_CS0 must be pulled down to Vss when attaching a Synchronous

 

 

 

 

Intel StrataFlash® on Chip Select 0 since the default mode for EXP_TIMING_CS0 is

 

 

 

 

Intel mode and EX_IOWAIT_N is an unknown value for Synchronous Intel

 

EX_ADDR[10]

 

IOWAIT_CS0

StrataFlash.

 

 

 

 

 

If the board does not connect the Synchronous Intel StrataFlash WAIT pin to

 

 

 

 

EX_WAIT_N (and the board guarantees EX_IOWAIT_N is pulled up), the value of

 

 

 

 

IOWAIT_CS0 is a don’t-care, since EX_IOWAIT_N will not be asserted.

 

 

 

 

When EXP_TIMING_CS0 is reconfigure to Intel Synchronous mode during boot-up

 

 

 

 

(for synchronous Intel chips), the expansion bus controller ignores EX_IOWAIT_N

 

 

 

 

during read and write cycles since the WAIT functionality is determined from the

 

 

 

 

EXP_SYNCINTEL_COUNT and EXP_TIMING_CS registers.

 

 

 

 

 

 

EX_ADDR[9]

 

EXP_MEM_DRIVE

Refer to table found in EX_ADDR[5].

 

 

 

 

 

 

 

 

 

Controls the USB clock select.

 

 

 

 

1 = USB Host/Device clock is generated internally

 

EX_ADDR[8]

 

USB Clock

0 = USB Device clock is generated from GPIO[0].

 

 

USB Host clock is generated from GPIO[1]. When generating a spread spectrum

 

 

 

 

 

 

 

 

clock on OSC_IN, GPIO[0] can be driven from the system board to generate a

 

 

 

 

48-MHz clock for the USB Device and GPIO[1] can be driven from the system board

 

 

 

 

to generate a 60-MHz clock for the USB Host.

 

 

 

 

 

 

EX_ADDR[7]

 

32_FLASH

Refer to table found in EX_ADDR[0]

 

 

 

 

 

 

 

 

 

Configures the Expansion bus arbiter.

 

EX_ADDR[6]

 

EXP_ARB

0 = External arbiter for Expansion bus.

 

 

 

 

1 = Expansion bus controller arbiter enabled

 

 

 

 

 

 

 

 

 

Expansion bus low/medium/high drive strength. The drive strength depends on

 

 

 

 

EXP_DRIVE and EXP_MEM_DRIVE configuration bits.

 

 

 

 

B9. B5

 

 

EX_ADDR[5]

 

EXP_DRIVE

---------------------------------------------------------------------------------------

 

 

0

. . 0

Reserved

 

 

 

 

 

 

 

 

0

. . 1 Medium Drive

 

 

 

 

1

. . 0

Low Drive

 

 

 

 

1

. . 1

High Drive

 

 

 

 

 

 

 

 

 

Sets the clock speed of the PCI Interface

 

EX_ADDR[4]

 

PCI_CLK

0 = 33 MHz

 

 

 

 

 

1 = 66 MHz

 

 

 

 

 

 

 

EX_ADDR[3]

 

(Reserved)

(Reserved). EX_ADDR[3] must not be pulled down during address strapping.

 

 

 

 

 

 

 

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

 

HDD

February 2007

22

Document Number: 305261; Revision: 004

Page 21 Page 23
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Page 21 Page 23
Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #List of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen DdrircompDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function Description3 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleSram Interface Uart InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsDevice Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorPower Interface Sheet 1 PowerName Nominal Description Voltage De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-CouplingHDD HDD General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAMII Signal Considerations Smii Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD @33 MHz Electrical InterfaceTopology @66 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesIntroduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitrySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock GroupParameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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