Intel IXP46X, IXP45X manual Resistive Compensation Register Rcomp, Clock Group

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

In addition to any trace length differentials which must be considered between signal groups, differences in the package length between signals should be considered when determining the total propagation delay of the signals. When using the IBIS model for signal analysis, package characteristics are included in the simulation results.

7.1.6Resistive Compensation Register (Rcomp)

Critical signals such as the differential clock drivers used for driving clock out to memory devices is very critical. The JEDEC standard has a very critical requirement for the crossing of the differential clock signals which required proper termination and drive strength of the signals. Therefore, in order to comply with this requirement, two recommendations have been made.

•Use Thevenin termination as shown in Figure 37. It is important that the series termination and impedance matching is strictly follow.

•Configuration of the Rcomp circuit.

The steps to follow and the order in which they need to occur to configure Rcomp are described in section “DDRI SDRAM Initialization” of the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual. Here is a recap of the two registers that are required to be overwritten with the new value:

•Override default value of register DDR_RCOMP_CSR3 with 0x0000 1000Hex

•Override default value of register DDR_DRIVE3 with 0x0002 08F0Hex

Note that this configuration only affects the SDRAM differential clock driver for all three outputs DDRI_CK[2:0] and DDRI_CK_N[2:0].

Refer to the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for the complete sequence of steps to follow to configure the SDRAM DDRI memory module.

Note that when simulating, the IBIS model representation of signals DDRI_CK[2:0] and DDRI_CK_N[2:0] has been created for the new Rcomp settings described in this section.

7.1.7Routing Guidelines

7.1.7.1Clock Group

The clock signal group includes the differential clock pairs DDRI_CK[2:0] and DDRI_CK_N[2:0].

Here are some tips on how to route the differential clock pairs:

•Ensure that DDR clocks are routed on a single internal layers, except for pin escapes.

•A ground plane must be adjacent to the layer where the signals are routed.

•Minimize the number of vias used, but ensure that the same number of vias are used in the positive and negative trace.

•It is recommended that pin escape vias be located directly adjacent to the ball pads on all clocks.

•Traces must be routed for differential mode impedance of 120 Ω.

•Surface layer routing should be minimized (top or bottom layers).

•It is recommended to perform pre- and post-layout simulation.

Table 34 provides routing guidelines for signals within this group.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

 

HDD

February 2007

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Document Number: 305261, Revision: 004

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Contents Hardware Design Guidelines FebruaryHDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics TablesRevision History Date Revision DescriptionHDD Content Overview Chapter Name DescriptionRelated Documentation Title Document #List of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications DslamSystem Architecture Description System Memory MapIntel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn DdrircompDDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function Description3 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface ExampleSram Interface Uart InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output DownMII/SMII Interface Uart Interface ExampleMII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal RecommendationsDevice Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, CGpio Interface Device Connection, SmiiGpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection USB Interface I2C Eeprom Interface ExampleUSB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface ExampleUtopia Signal Recommendations HSS Interface Utopia Interface ExampleHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2Supporting 5 V PCI Interface PCI InterfacePCI Option Interface PCI Host/Option Interface Pin Description Sheet 1PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorPower Interface Sheet 1 PowerName Nominal Description Voltage Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-CouplingHDD HDD Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAMII Signal Considerations Smii Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design ConsiderationsPower and Ground Plane Trace ImpedanceHDD Electrical Interface Topology@33 MHz @66 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40DDR Sdram HDD Supported Memory Configurations Clock Banks Memory SizeVTT Selecting VTT Power Supply VTT Terminating CircuitrySymbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing ParametersPrinted Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer StackupPrinted Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock GroupClock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, DdriwenClock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line LengthDDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 DevicesData Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control GroupDDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line CharacteristicsDDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT TopologyDDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108
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