Texas Instruments TNETX4090 specifications Port to not support pause frames

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

					Terminal Functions (Continued)
100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode]

	TERMINAL		I/O	INTERNAL			DESCRIPTION
	NAME		I/O	RESISTOR			DESCRIPTION
	NAME			RESISTOR

					Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision.
	M08_COL		I	Pulldown	Additionally, during full-duplex operation, transmission of new frames does not commence if this
					terminal is asserted.

	M08_CRS		I	Pulldown	Carrier sense. M08_CRS indicates a frame carrier signal is being received.

	M08_EWRAP		O	None	Enable wrap. M08_EWRAP reflects the state of the loopback bit in the PCS8Control register.

	M08_GTCLK		O	None	Unused. This terminal can be left unconnected.

					Connection status. M08_LINK indicates the presence of port connection.
	M08_LINK		I	Pulldown	± If M08_LINK = 0, there is no link.
					± If M08_LINK = 1, the link is OK.

					Renegotiate.		indicates to the attached PHY device that this device wishes to negotiate
					Renegotiate.	M08_LREF
					a new configuration.

			O	None	± Following a 0-to-1 transition of neg in PortxControl,			M08_LREF	is asserted low, and
	M08_LREF		O	None	remains low until M08_LINK goes low. If M08_LINK was already low, M08_LREF is still
					activated for at least one cycle.
					± M08_LREF is asserted low for as long as initd in SysControl = 0, regardless of the state
					of M08_LINK.

	M08_RCLK		I	Pullup	Receive clock. Receive clock source from the attached PHY or PMI device.

	M08_RFCLK		I	Pullup	Transmit clock. Transmit clock from the attached PHY or PMI device.

	M08_RXD7		I	Pullup	Unused. These terminals can be left unconnected.
	M08_RXD6		I	Pullup	Unused. These terminals can be left unconnected.
	M08_RXD6

					IEEE Std 802.3x pause frame support selection
	M08_RXD5		I/O²	Pullup	± If pulled low either internally or by the attached PHY or PMI device, M08_RXD5 causes the
					port to not support pause frames.
					± If not pulled low, the port does not support pause frames.

					Duplex selection [force half duplex (active low)]
	M08_RXD4		I/O²	Pullup	± If pulled low either internally or by the attached PHY or PMI device, the port operates in
					half-duplex mode.
					± If not pulled low, the port operates in full-duplex mode.

	M08_RXD3
	M08_RXD2		I	Pullup	Receive data. Nibble-wide receive data from the attached PHY or PMI device. When M08_RXDV
	M08_RXD1		I	Pullup	is asserted, these signals carry receive data. Data on these signals is synchronous to M08_RCLK.
	M08_RXD1
	M08_RXD0

	M08_RXDV		I	Pulldown	Receive data valid. M08_RXDV indicates data on M08_RXD3±M08_RXD0 is valid. This signal is
	M08_RXDV		I	Pulldown	synchronous to M08_RCLK.
					synchronous to M08_RCLK.

	M08_RXER		I	Pulldown	Receive error. Indicates reception of a coding error on received data.

	M08_TXD7
	M08_TXD6		O	None	Unused. These terminals can be left unconnected, but are driven low.
	M08_TXD5		O	None
	M08_TXD5
	M08_TXD4

	M08_TXD3
	M08_TXD2		O	None	Transmit data. Nibble-wide transmit data. When M08_TXEN is asserted, these signals carry
	M08_TXD1		O	None	transmit data. Data on these signals is synchronous to M08_RFCLK.
	M08_TXD1
	M08_TXD0

²Not a true bidirectional terminal. It can only be actively pulled down.

10	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice