Texas Instruments TNETX4090 Transmit Pretag Bit Definitions, Pretag on reception, M08RCLK M08RXDV

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TNETX4090

 

 

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

 

 

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

 

 

 

 

 

 

Table 10. Transmit Pretag Bit Definitions

 

 

 

 

BIT

NAME

FUNCTION

 

 

 

 

 

31±28

reserved

Reserved. These bits always are 0.

 

 

 

 

 

 

 

Receive header. Indicates whether an IEEE Std 802.1Q header was added to the frame on reception.

 

27

rxheader

± When rxheader = 1, an IEEE Std 802.1Q header was inserted.

 

 

 

± When rxheader = 0, no IEEE Std 802.1Q header was inserted.

 

 

 

 

 

26±25

reserved

Reserved. These bits always are 0.

 

 

 

 

 

24±20

portcode

Source port code. Indicates which port on the device received the frame. Codes 00000±01001 indicate ports 0±9,

 

respectively (port 9 is the NM DIO port). All other codes are reserved and are not generated.

 

 

 

 

 

 

 

 

19±17

reserved

Reserved. These bits always are 0.

 

 

 

 

 

16±0

xportvector²

Extended destination port vector. A bit for each port on the crossbar matrix. A 1 in position n indicates the frame is

 

destined for port n on the crossbar matrix.

 

 

 

 

 

 

 

 

²Bit vector, in which bit x corresponds to external crossbar matrix port x. Any number of ports can be selected at the same time.

pretag on reception

Port 8 can receive two tag formats, learning and directed, over eight cycles, beginning with the first cycle that M08_RXDV is high. The pretag takes the form of a 32-bit value (divided into eight nibbles), with each nibble being replicated on M08_RXD3±M08_RXD0 and M08_RXD7±M08_RXD4. This replaces the preamble and sof delimiter normally received at this time.

Figure 6 shows the timing relationship, and Table 11 and Table 12 show the fields within the tag for learning and directed format, respectively.

M08_RCLK

M08_RXDV

M08_RXD3±

3±0

7±4

11±8

15±12

19±16

23±20

27±24

31±28

Frame Data

M08_RXD0

 

 

 

 

 

 

 

 

 

M08_RXD7±

 

 

 

 

 

 

Frame Data

M08_RXD4

 

 

 

 

 

 

NOTE: Ranges (e.g., 3±0) indicate which bits of the 32-bit pretag are input in each cycle.

 

 

Figure 6. Receive Pretag Timing

 

 

Table 11. Learning Format Receive Pretag Bit Definitions

 

 

 

BIT

NAME

FUNCTION

 

 

 

 

 

Zero. Indicates learning format. Frames received with this tag format are routed using the device internal frame-routing

31

0

algorithm. When the source address is learned, the crossbar matrix port number, indicated by xportcode, also is

learned, and is used to create the xportvector output as part of the transmit pretag for frames subsequently routed to

 

 

 

 

this address.

 

 

 

30±5

reserved

Reserved. Bits 30±5 are ignored.

 

 

 

4±0

xportcode³

Source port code. Portcode indicates which port on the device received the frame. Codes 00000±10000 indicate

ports 0±16, respectively. All other codes are reserved and are not generated.

 

 

 

 

 

³Binary code that selects a single port on this device or an external crossbar matrix connected to port 8

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Contents Description DMA MIIMAC MII MAC Eeprom CPU I/FPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interfaceM08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailReceiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup StatisticsIeee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware ResetCRC Vlan IDFCS Tpid TCITNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priorityMAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement BackoffSpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow controlPretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit DefinitionsTNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes State Display Compatibility with future device revisionsPort LED States Collision LED StatesMulti-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp testSout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDDJtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instructionFrame routing Vlan supportIale Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmissionAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingExtended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports RegisterFlow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limitInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii port Gmii receive see FigureGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureDbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk DrxclkDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice
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