Texas Instruments TNETX4090 Port Statistics, Tail, Port no Head Statistic Even ODD Ports

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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

Table 3. Port Statistics 1

				TAIL
	PORT NO.	HEAD	STATISTIC
	PORT NO.	HEAD	STATISTIC	EVEN	ODD
				PORTS	PORTS

	0	0x80xx	Receive octet	00	80

	1	0x80xx	Good receive frames	04	84

	2	0x81xx	Broadcast receive frames	08	88

	3	0x81xx	Multicast receive frames	0C	8C

	4	0x82xx	Receive CRC errors	10	90

	5	0x82xx	Receive align/code errors²	14	84
	6	0x83xx	Oversized receive frames	18	98

	7	0x83xx	Receive jabbers	1C	9C

	8	0x84xx	Undersized receive frames	20	A0

	NM	0x84xx	Receive fragments	24	A4

		0x85xx	64-octet frames	28	A8

		0x85xx	65±127 octet frames	2C	AC

		0x86xx	128±255 octet frames	30	B0

		0x86xx	256±511 octet frames	34	B4

		0x87xx	512±1023 octet frames	38	B8

		0x87xx	1024±1518 octet frames	3C	BC

		0x88xx	Net octets	40	C0

		0x88xx	SQE test errors²	44	C4
		0x89xx	Tx octets	48	C8

		0x89xx	Good transmit frames	4C	CC

	Reserved	0x8Axx	Single-collision transmit frames²	50	D0
	Reserved	0x8Axx	Multiple-collision transmit frames²	54	D4
		0x8Axx	Multiple-collision transmit frames²	54	D4
		0x8Bxx	Carrier sense errors²	58	D8
		0x8Bxx	Deferred transmit frames²	5C	DC
		0x8Cxx	Late collisions²	60	E0
		0x8Cxx	Excessive collisions²	64	E4
		0x8Dxx	Broadcast transmit frames	68	E8

		0x8Dxx	Filtered receive frames	6C	EC

		0x8Exx	Filtered receive frames	70	F0

		0x8Exx	Transmit data errors	74	F4

		0x8Fxx	Collisions²	78	F8
		0x8Fxx	Receive overruns	7C	FC

²The NM port does not have this statistic. This address is reserved on the NM port.

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Contents Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice