Texas Instruments TNETX4090 specifications DIO interface, DIO and DMA writes see Figure

Page 69

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

DIO interface

The DIO interface is simple and asynchronous to allow easy adaptation to a range of microprocessor devices and computer system interfaces.

DIO and DMA writes (see Figure 25)

NO.

MIN

MAX

UNIT

1

tw(SCS)

Pulse duration,

↓

2tc

ns

SCS

2

tsu(SRNW)

Setup time, SRNW valid before

↓

0

ns

SCS

3

tsu(SAD)

Setup time, SAD1±SAD0,

valid before

↓

0

ns

SDMA

SCS

4

tsu(SDATA)

Setup time, SAD7±SAD0 valid before

↓

0

ns

SCS

5

th(SRNW)

Hold time, SRNW low after

↓

0

ns

SRDY

6

th(SAD)

Hold time, SAD1±SAD0,

valid after

↓

0

ns

SDMA

SRDY

7

th(SDATA)

Hold time, SAD7±SAD0 valid after

↓

0

ns

SRDY

8

th(SCSL)

Hold time,

low after

↓

0

ns

SCS

SRDY

9

td(SRDYZH)

Delay time from

↓ to

↑

10

ns

SCS

SRDY

10

td(SRDYHL)

Delay time from

↓ to

↓

2tc

²

ns

SCS

SRDY

11

td(SRDYLH)

Delay time from

↑ to

↑

tc

2tc+10

ns

SCS

SRDY

12

th(SCSH)

Hold time,

high after

↑

0

ns

SCS

SRDY

13

tw(SRDY)

Pulse duration,

↑

tc

ns

SRDY

14

td(SINT)

Delay time from

↓ to SINT valid. (write to INT or INT_Enable register)

2tc

ns

SRDY

²When the switch is performing certain internal operations (e.g., EEPROM load), there is a delay of up to 20 ms (24C02) or 800 ms (24C08) between SCS being asserted and SRDY being asserted.

4 10

3 1

2

9

8

11

12

SCS

5

SRNW

6

SAD1±SAD0

SDMA

7

SDATA7±

SDATA0

13

SRDY

14

SINT

Figure 25. DIO and DMA Writes

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Image 69

Contents Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomePretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusFrame routing Vlan supportIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii port Gmii receive see FigureGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice