Texas Instruments TNETX4090 Gmii port, Gmii receive see Figure, Gmii transmit see Figure

Page 64

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

GMII (port 8)

Figures 18±20 show the timing for the 100-/1000-Mbit/s GMII when operating at 1000 Mbit/s.

Both Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD7±MxxRXD0 is driven by the PHY on the falling edge of Mxx_RCLK. Mxx_RXD7±MxxRXD0 timing must be met during clock periods in which Mxx_RXDV is asserted. Mxx_RXDV is asserted and deasserted by the PHY on the falling edge of Mxx_RCLK. Mxx_RXER is driven by the PHY on the falling edge of Mxx_RCLK.

GMII receive (see Figure 18)

NO.			MIN MAX	UNIT

1	tsu(Mxx_RXD)	Setup time, Mxx_RXD7±Mxx_RXD0 valid before Mxx_RCLK↑	2	ns
1	tsu(Mxx_RXDV)	Setup time, Mxx_RXDV valid before Mxx_RCLK↑	2	ns
1	tsu(Mxx_RXER)	Setup time, Mxx_RXER valid before Mxx_RCLK↑	2	ns
2	th(Mxx_RXD)	Hold time, Mxx_RXD7±Mxx_RXD0 valid after Mxx_RCLK↑	1	ns
2	th(Mxx_RXDV)	Hold time, Mxx_RXDV valid after Mxx_RCLK↑	1	ns
2	th(Mxx_RXER)	Hold time, Mxx_RXER valid after Mxx_RCLK↑	1	ns

Mxx_RCLK

1 2

Mxx_RXD7±Mxx_RXD0

Mxx_RXDV

Mxx_RXER

Figure 18. GMII Receive

Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_GTCLK is derived directly from Mxx_RFCLK. Mxx_TXD7±Mxx_TXD7 is driven by the reconciliation sublayer synchronous to the Mxx_GTCLK. Mxx_TXEN is asserted and deasserted by the reconciliation sublayer synchronous to the Mxx_GTCLK rising edge. Mxx_TXER is driven synchronous to the rising edge of Mxx_GTCLK.

GMII transmit (see Figure 19)

NO.

MIN

MAX

UNIT

1

td(Mxx_TXD)

Delay time, from Mxx_GTCLK↑ to Mxx_TXD3±MxxTXD0 valid

1.5

4.5

ns

1

td(Mxx_TXEN)

Delay time, from Mxx_GTCLK↑ to Mxx_TXEN valid

1.5

4.5

ns

1

td(Mxx_TXER)

Delay time, from Mxx_GTCLK↑ to Mxx_TXER valid

1.5

4.5

ns

Mxx_GTCLK

Mxx_TXD7±Mxx_TXD0

1

Mxx_TXEN

Mxx_TXER

Figure 19. GMII Transmit

64	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 64

Contents Description MII MAC MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExDMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management framesState of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portVlan ID FCSTpid TCI CRCTNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processingMAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name FunctionDirected Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Compatibility with future device revisions Port LED StatesCollision LED States State DisplayPCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayBUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDJtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist StatusVlan support Frame routingIale Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portPort trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX Unit Reset see Figure Jtag interface Control signals Timing requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureRdram interface Rdram see FigureDtxclk Drxclk Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice