Texas Instruments TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch

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TNETX4090

 

 

 

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

 

 

 

 

 

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions (Continued)

10-/100-Mbit/s MAC interface (MII mode) (ports 0±7) (continued)

 

 

 

 

 

 

 

TERMINAL

 

I/O

INTERNAL

 

DESCRIPTION

 

NAME

NO.

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

M00_RXER

C19

 

 

 

 

 

M01_RXER

C14

 

 

 

 

 

M02_RXER

B9

 

 

 

 

 

M03_RXER

B4

I

Pulldown

 

Receive error. Indicates reception of a coding error on received data.

 

M04_RXER

L4

 

 

 

 

 

 

 

M05_RXER

T3

 

 

 

 

 

M06_RXER

AA2

 

 

 

 

 

M07_RXER

AD8

 

 

 

 

 

 

 

 

 

 

 

 

M00_TCLK

B23

 

 

 

 

 

M01_TCLK

C17

 

 

 

 

 

M02_TCLK

C13

 

 

 

 

 

M03_TCLK

A8

I

Pullup

 

Transmit clock. Transmit clock source from the attached PHY or PMI device.

 

M04_TCLK

F1

 

 

 

 

 

 

 

M05_TCLK

L2

 

 

 

 

 

M06_TCLK

T1

 

 

 

 

 

M07_TCLK

AD4

 

 

 

 

 

 

 

 

 

 

 

 

M00_TXD3

C22

 

 

 

 

 

M00_TXD2

B22

 

 

 

 

 

M00_TXD1

A22

 

 

 

 

 

M00_TXD0

A23

 

 

 

 

 

M01_TXD3

C18

 

 

 

 

 

M01_TXD2

B18

 

 

 

 

 

M01_TXD1

A18

 

 

 

 

 

M01_TXD0

A19

 

 

 

 

 

M02_TXD3

D12

 

 

 

 

 

M02_TXD2

C12

 

 

 

 

 

M02_TXD1

B12

 

 

 

Transmit data. Byte transmit data. When Mxx_TXEN is asserted, these signals carry

 

M02_TXD0

A12

 

 

 

 

 

 

 

transmit data. Data on these signals is synchronous to Mxx_TCLK. When Mxx_TXEN,

 

M03_TXD3

D7

 

 

 

 

 

 

 

Mxx_TXER, and Mxx_LINK are all low, these terminals indicate the desired capabilities for

 

M03_TXD2

C7

 

 

 

 

 

 

 

autonegotiation as follows:

 

M03_TXD1

B7

 

 

 

 

 

 

 

± Mxx_TXD0 indicates full-duplex capability when high; half duplex when low, as

 

M03_TXD0

A7

O

None

 

 

 

determined by reqhd in PortxControl.

 

M04_TXD3

G4

 

 

 

 

 

± Mxx_TXD1 indicates IEEE Std 802.3 pause frame support when high; no pause

 

M04_TXD2

G3

 

 

 

 

 

 

 

when low, as determined by reqnp in PortxControl.

 

M04_TXD1

G2

 

 

 

 

 

 

 

± Mxx_TXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, as determined by

 

M04_TXD0

G1

 

 

 

 

 

 

 

req10 in PortxControl.

 

M05_TXD3

M4

 

 

 

 

 

 

 

± Mxx_TXD3 is unused and is 0.

 

M05_TXD2

M3

 

 

 

 

 

 

 

 

 

M05_TXD1

M2

 

 

 

 

 

M05_TXD0

M1

 

 

 

 

 

M06_TXD3

U4

 

 

 

 

 

M06_TXD2

U3

 

 

 

 

 

M06_TXD1

U2

 

 

 

 

 

M06_TXD0

U1

 

 

 

 

 

M07_TXD3

AC5

 

 

 

 

 

M07_TXD2

AD5

 

 

 

 

 

M07_TXD1

AE5

 

 

 

 

 

M07_TXD0

AF5

 

 

 

 

 

 

 

 

 

 

 

 

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Contents Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice
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