Texas Instruments TNETX4090 specifications Physical medium attachment interface port Receive

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

physical medium attachment interface (port 8)

receive

PMA receive (see Figure 16)

NO.			MIN	MAX	UNIT

1	tc(Mxx_RBC)	Cycle time, receive byte clock 0 and 1 (Mxx_RCLK, Mxx_COL)	16	16	ns
±	t	Drift rate² of receive bye clock 0 and 1	0.2		ns
	drift(Mxx_RBC)
2,3	tw(Mxx_RBC)	Pulse duration, Mxx_RCLK, Mxx_COL low or high	40%	60%	ns
4	tsu(Mxx_RXD)	Setup time, Mxx_RXD7±Mxx_RXD0 valid before Mxx_RCLK/COL↑	2.5		ns
4	tsu(Mxx_RXDV)	Setup time, Mxx_RXDV valid before Mxx_RCLK/COL↑	2.5		ns
4	tsu(Mxx_RXER)	Setup time, Mxx_RXER valid before Mxx_RCLK/COL↑	2.5		ns
5	th(Mxx_RXD)	Hold time, Mxx_RXD7±Mxx_RXD0 valid after Mxx_RCLK/COL↑	1.5		ns
5	th(Mxx_RXDV)	Hold time, Mxx_RXDV valid after Mxx_RCLK/COL↑	1.5		ns
5	th(Mxx_RXER)	Hold time, Mxx_RXER valid after Mxx_RCLK/COL↑	1.5		ns
6	tskew(Mxx_RBC)	Skew between receive byte clock 1 and receive byte clock 0	7.5	8.5	ns

²tdrift is the (minimum) time for either RBC0 or RBC1 to drift from 63.5 MHz to 64.5 MHz or 60 Mhz to 59 MHz from their lock value. It is applicable under all input signal conditions (except under certain circumstances during comma detection), including invalid or absent input signals, if the receiver clock recovery unit was previously locked to Mxx_RFCLK or to a valid input signal.

	1
	6
2	3	5
		4

Receive Byte

Clock 0

Receive

Code Group

Comma Detect

Receive Byte

Clock 0

Figure 16. PMA Receive

4

5

Data Group

62	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 62

Contents Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interface100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomeM08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDM08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusIale Frame routingVlan support Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitTiming requirements over recommended operating conditions Jtag interface Control signalsReset see Figure Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii transmit see Figure Gmii portGmii receive see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice