Texas Instruments TNETX4090 specifications Port 8 Duplex Negotiation in MII Mode, Outcome

Page 37

TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

speed, duplex, and flow-control negotiation (continued)

In 100-Mbit/s mode, M08_RXD4 and M08_RXD5 are reconfigured as open-drain inputs, to allow the port to negotiate with the PHY device for duplex and IEEE Std 802.3 pause frame support at power up via the EEPROM contents. M08_RXD4 is used for duplex and M08_RXD5 is used for pause (see Table 8 and Table 9).

Each of these terminals:

DHas an integral weak pullup resistor.

DHas a strong open-drain pulldown transistor that is enabled by setting to 1 the appropriate bit in Port8Control.

DIs connected (via synchronization logic) to the appropriate bit in PortxStatus. These bits directly control the configuration of the ports.

Each terminal is considered bidirectional when pulled low by either the TNETX4090 or by the PHY (or other external connections). If neither pulls the terminal low, the pullup resistor maintains a value of 1 on the terminal. When the PHY does not pull down a terminal, it can determine the desired option being requested by the TNETX4090. The TNETX4090 observes the terminal to determine if its desired option has been granted.

The sense of these signals is such that the higher-performance option is represented by a value of 1, so if the MAC does not require the higher performance or the PHY cannot supply it, either can pull the signal low, forcing the port to use the lower-performance option.

The status of the link for this port is indicated on M08_LINK and is observable in Port8Status. M08_LINK plays no part in the negotiation of pause or duplex or their recording in Port8Status.

Table 8. Port 8 Duplex Negotiation in MII Mode

Port8Control

 

M08_RXD4

 

Port8Status

OUTCOME

reqhd

 

 

duplex

 

 

 

 

 

 

 

 

 

 

0

→

Floating 1

→

1

Full duplex

 

 

 

 

 

 

1

→

Driven 0 (by the TNETX4090)

→

0

Half duplex

 

 

 

 

 

 

X

 

Driven 0 (by PHY)

→

0

Half duplex

 

 

 

 

 

 

Table 9. Port 8 Pause Negotiation in MII Mode

Port8Control

 

M08_RXD5

 

Port8Status

OUTCOME

reqnp

 

 

pause

 

 

 

 

 

 

 

 

 

 

0

→

Floating 1

→

1

Pause support

 

 

 

 

 

 

1

→

Driven 0 (by the TNETX4090)

→

0

No pause support

 

 

 

 

 

 

X

 

Driven 0 (by PHY)

→

0

No pause support

 

 

 

 

 

 

full-duplex hardware flow control

This port provides hardware-level full-duplex flow control via the M08_COL and FLOW terminals.

DThe port does not start transmitting a new frame if M08_COL is active, though the value of this terminal is ignored at other times.

DFLOW becomes active when the number of free buffers is fewer than the number specified in FlowThreshold, provided that flow in SysControl is set.

These two capabilities allow full-duplex flow control without the use of IEEE Std 802.3 pause frames when connecting the TNETX4090 to another TNETX4090, or to some other device that supports this capability.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

37

Page 36 Page 38
Image 37
Page 36 Page 38
Contents Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice
Top Page Image Contents