Texas Instruments TNETX4090 specifications

Page 22

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3	BYTE 2		BYTE 1	BYTE 0	DIO
BYTE 3	BYTE 2		BYTE 1	BYTE 0	ADDRESS
					ADDRESS

		XMultiGroup19			0x054C

		XMultiGroup20			0x0550

		XMultiGroup21			0x0554

		XMultiGroup22			0x0558

		XMultiGroup23			0x055C

		XMultiGroup24			0x0560

		XMultiGroup25			0x0564

		XMultiGroup26			0x0568

		XMultiGroup27			0x056C

		XMultiGroup28			0x0570

		XMultiGroup29			0x0574

		XMultiGroup30			0x0578

		XMultiGroup31			0x057C

		XMultiGroup32			0x0580

		XMultiGroup33			0x0584

		XMultiGroup34			0x0588

		XMultiGroup35			0x058C

		XMultiGroup36			0x0590

		XMultiGroup37			0x0594

		XMultiGroup38			0x0598

		XMultiGroup39			0x059C

		XMultiGroup40			0x05A0

		XMultiGroup41			0x05A4

		XMultiGroup42			0x05A8

		XMultiGroup43			0x05AC

		XMultiGroup44			0x05B0

		XMultiGroup45			0x05B4

		XMultiGroup46			0x05B8

		XMultiGroup47			0x05BC

		XMultiGroup48			0x05C0

		XMultiGroup49			0x05C4

		XMultiGroup50			0x05C8

		XMultiGroup51			0x05CC

		XMultiGroup52			0x05D0

		XMultiGroup53			0x05D4

		XMultiGroup54			0x05D8

		XMultiGroup55			0x05DC

		XMultiGroup56			0x05E0

		XMultiGroup57			0x05E4

		XMultiGroup58			0x05E8

		XMultiGroup59			0x05EC

		XMultiGroup60			0x05F0

22	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 22

Contents Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice