Texas Instruments TNETX4090 specifications Port trunking/load sharing, Removal of source port

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

removal of source port

Normally, the IALE does not route a frame to a port on which it was received. The port routing code is examined to see if the source port is included. If so, the port routing code is modified to remove the source port.

If the bit in RingPorts corresponding to the port that received the frame is set, the port routing code is not modified to remove the source port. This is required for connecting the port to other like switches in a ring topology.

If the source port is a member of a trunk (see Trunking), then all the other ports that are members of the same trunk also are removed from the port routing code.

port mirroring

It is possible to copy (or mirror) all frames that are received by and transmitted from a port to another designated port, using the mirror port register.

It also is possible to mirror frames destined for a particular MAC address by using the copy-uplink feature. When a frame specifies the destination address with the copy-uplink feature enabled, frames are copied to the specified port.

copy-to-uplink (cuplink)

If destination address is a unicast and the cuplink bit of its address record has been set to a 1 (via a DIO add), and when a frame specifies that destination, a copy of the frame is sent to the port specified in the UplinkPort register.

port trunking/load sharing

Trunking allows two or more ports to be connected in parallel between switches to increase the bandwidth between those devices. The trunking algorithm determines on which of these ports a frame is transmitted, so that the load is spread evenly across these ports.

The TNETX4090 supports a maximum of four trunk groups for the 10-/100-Mbit ports. The port members of a trunk group are software configurable via the DIO interface. Trunk-port determination is the final step in the IALE frame-routing algorithm. Once the destination port(s) for a frame have been determined, the port routing code is examined to see if any of the destination port(s) are members of a trunk. If so, the trunking algorithm is applied to select the port within the trunk that transmits the frame ± it may or may not be the one currently in the port routing code. To determine the destination port within a trunk, bits 3±1 of the source and destination address are XORed to produce a map index. This map index is used to index to a group of eight internal registers to determine the destination port (for details see the TNETX4090 Programmer's Reference Guide, literature number SPAU003). Port trunking uses the destination/source address pairs to route the traffic to balance the load more evenly across the trunked ports. Since the same destination/source address pair always uses the same port to route the traffic, this also makes it much easier to debug network problems.

Load sharing is similar to trunking , but with two slight differences. It uses the trunking algorithm only once when the destination address is unknown. Once the destination address has been learned, it uses the port routing code associated with the destination address.

If the destination is unknown, the map index is derived from only the source address. If a server is communicating with a large number of different clients, then, since the source address is the same, it is possible to have very poor traffic distribution.

DIf the destination address is found in the IALE records when it is looked up, the port routing code is not adjusted by the load-sharing algorithm.

DThe 3-bit map index is determined only from the source address, as follows:

±Bits 47±32 are XORed to produce the most significant bit of the map index.

±Bits 31±16 are XORed to produce the middle of the map index.

±Bits 15±0 are XORed to produce the least significant bit of the map index.

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Contents Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomePretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusFrame routing Vlan supportIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii port Gmii receive see FigureGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice
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