Texas Instruments TNETX4090 10-/100-Mbit/s MAC interface MII mode ports 0±7, Pulldown

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

Terminal Functions (Continued)

100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] (continued)

TERMINAL

I/O

INTERNAL

DESCRIPTION

NAME

RESISTOR

 

 

 

 

 

 

M08_TXEN

O

None

Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD3±M08_TXD0. This signal

is synchronous to M08_RFCLK.

 

 

 

 

 

 

 

 

 

 

Transmit error. M08_TXER allows coding errors to be propagated between the MAC and the

M08_TXER

O

None

attached PHY. It is asserted at the end of an under-running frame, enabling the device to force a

 

 

 

coding error.

 

 

 

 

10-/100-Mbit/s MAC interface (MII mode) (ports 0±7)

TERMINAL

 

I/O

INTERNAL

DESCRIPTION

NAME

NO.

RESISTOR

 

 

 

 

 

 

 

M00_COL

C21

 

 

 

M01_COL

D16

 

 

 

M02_COL

C11

 

 

Collision sense. Assertion of Mxx_COL indicates network collision. In full-duplex mode, the

M03_COL

A6

 

 

I

Pulldown

port does not start transmitting a new frame if this signal is active; the value of this terminal

M04_COL

H2

 

 

is ignored at all other times.

M05_COL

N2

 

 

 

 

 

M06_COL

V1

 

 

 

M07_COL

AC6

 

 

 

 

 

 

 

 

M00_CRS

B21

 

 

 

M01_CRS

C16

 

 

 

M02_CRS

B11

 

 

 

M03_CRS

B6

I

Pulldown

Carrier sense. Indicates a frame-carrier signal is being received.

M04_CRS

H1

 

 

 

M05_CRS

P3

 

 

 

M06_CRS

W3

 

 

 

M07_CRS

AD6

 

 

 

 

 

 

 

 

M00_LINK

B19

 

 

 

M01_LINK

B14

 

 

Connection status. Indicates the presence of port connection:

M02_LINK

A9

 

 

 

 

± If Mxx_LINK = 0, there is no link.

M03_LINK

A4

I

Pulldown

M04_LINK

L3

± If Mxx_LINK = 1, the link is OK.

 

 

M05_LINK

T2

 

 

An internal pullup resistor is provided.

M06_LINK

AA1

 

 

 

M07_LINK

AF3

 

 

 

 

 

 

 

 

M00_RCLK

A21

 

 

 

M01_RCLK

B16

 

 

 

M02_RCLK

A11

 

 

 

M03_RCLK

C6

I

Pullup

Receive clock. Receive clock source from the attached PHY device.

M04_RCLK

J3

 

 

 

M05_RCLK

P2

 

 

 

M06_RCLK

W2

 

 

 

M07_RCLK

AE6

 

 

 

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents Description DMA MIIMAC MII MAC Eeprom CPU I/FPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interfaceM08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interface100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail 0x90Ex Port no Head Statistic TailReceiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup StatisticsIeee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware ResetCRC Vlan IDFCS Tpid TCITNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priorityMAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement BackoffSpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow controlM08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit DefinitionsTNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXDM08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register State Display Compatibility with future device revisionsPort LED States Collision LED StatesMulti-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp testSout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDDJtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instructionIale Frame routingVlan support Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmissionAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingExtended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports RegisterFlow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limitInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsTiming requirements over recommended operating conditions Jtag interface Control signalsReset see Figure PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii transmit see Figure Gmii portGmii receive see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureDbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk DrxclkSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice
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