Texas Instruments TNETX4090 Other flow-control mechanisms, Hardware flow control, Multicast limit

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

other flow-control mechanisms

hardware flow control

If a port were in MII or GMII mode and full duplex, normally, its Mxx_COL would not be needed. Hardware flow control has been added by preventing the start of a frame transmission if the Mxx_COL is high. This is useful in ring mode; the Mxx_COL can be tied to the FLOW of the upstream neighbor for hardware flow control.

multicast limit

Because buffer resources for multicast (or broadcast) frames are released only when the last port has transmitted the frame, multicast packets to fast and slow ports are released at the slow-port rate. Multicast traffic from a fast port to a slow port could cause back pressure to be applied to the source port, blocking input from that port. This occurs even if at least one of the ports in the multicast could have kept pace with the inbound multicast packets. The MCastLimit register can limit the number of multicast packets allowed to be pending at any output port. When the limit is reached, that port is not added to the routing vector of the next multicast packet for which it was eligible. Eligibility is restored when the number of backlogged packets is again below the limit. MCastLimit allows the user to set the ports subject to this restriction, and set the limit in 8 binary steps, from 2 to 256. The spanning-tree BPDU multicast packet is exempt from this limit.

other behavior changes resulting from flow-control bits or terminals

Clearing (the default) holbrm in the RingPorts register includes the test for buffer use controlled by the holb bit in SysControl into the action of the FLOW terminal. FLOW goes high if either the number of buffers left is less than the FlowThreshold value or a ring-mode port receive operation has exceeded its fair share of buffers. Setting holbrm = 1 makes FLOW respond only to FlowThreshold value violations.

system test capabilities

RDRAM

The external RDRAM can be read and written using regular DIO accesses following a stop. Individual bytes can be read and written. However, as the RDRAM memory is actually accessed in 128-byte pages, performing 128-byte accesses is the most efficient.

To access the RDRAM, the TNETX4090 must not be operating. The user must perform a reset and not set start in SysControl. Both start and initd in SysControl must be 0. In addition, rdinit in SysTest must be set, indicating that the RDRAM has initialized. This initialization sequence occurs automatically after a hard reset.

Read or write accesses to RDRAM are invoked via rdram and rdwrite in SysTest. Setting rdram to 1 causes a 128-byte transfer between the device and the RDRAM memory to be initiated.

DThe transfer direction is determined by rdwrite.

DThe external memory byte address for the access is specified by ramaddress in RAMAddress.

DData to be read from or written to RDRAM is accessed indirectly via RAMData.

writing RDRAM

Writing to RDRAM memory is accomplished as follows:

1.Write the byte address for the access to ramaddress in RAMAddress.

2.Write the data for the access to RAMData. Up to 64 bytes can be written, if all but the six least significant bits of the address are the same for all the data. Inc in RAMAddress can be used to autoincrement the address.

3.Set rdwrite = 0 and rdram = 1 (these can be written simultaneously).

4.If required, poll rdram until it becomes 0. This indicates that the write has completed.

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Contents Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomePretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusFrame routing Vlan supportIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii port Gmii receive see FigureGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice
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