Texas Instruments TNETX4090 specifications Flow control

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

flow control

The TNETX4090 supports collision-based flow control for ports in half-duplex mode and IEEE Std 802.3x flow control for ports in full-duplex mode. The flow bit in the SysControl register determines the action that will be taken when back pressure is needed, that is, when there are insufficient resources to handle an inbound packet. The holb bit in the SysControl register determines when back pressure is needed.

DIf flow = 0, packets are discarded at the ingress port when insufficient resources are available to handle them.

DIf flow = 1, ports in half-duplex mode cause collisions to avoid accepting packets, ports in full-duplex mode whose link partners negotiated to accept pause packets will send them; otherwise, packets are dropped. If port 8 is in MII mode, the pause-frame transmission/reception is required to be symmetrical. If in GMII or PMA mode, transmit and receive pause capabilities are negotiated independently.

DWith holb = 0, back pressure is applied to all ports when the number of buffers in the global pool is down to the value in the FlowThreshold register (or half of this value if the packet arrives at a port in gigabit mode). This prevents the reception of more frames at any port until the frame backlog is reduced and the number of free buffers has risen above the threshold. When this happens, back pressure is removed from all ports and packets can be received. The value in FlowThreshold should be set so that all ports can complete reception of a maximum-size frame, that is, each port should have enough time to activate the flow mechanisms without dumping a frame for which reception has started.

DIf holb = 1, back pressure is applied as when holb = 0, or to an individual port when the buffers held in memory for data that arrived on that port is greater than the available pool remaining. Assume that FlowThreshold is set small enough that this mechanism does not affect the back pressure in this mode. An example is:

±When port A's traffic begins to backlog in memory [no matter to what port(s) it is destined], back pressure will be applied when the amount of data backed up is greater than the available pool (about half the buffers are assigned to data from port A). If A's data stays backlogged and if data arriving at port B also begins to backlog in memory, back pressure will be applied to port B when its data amounts to one-fourth of the buffer pool, or half of the half left after port A had back pressure applied. When port A's traffic begins to exit the switch, port A will stay back pressured until its data is equal to one third of the total. As buffers become available, port B will be allowed to consume up to one third of the buffer pool (each backlogged total is compared with the buffers available). In this mode, only the stations that have caused their fair share of buffers to be removed from the available pool will be back pressured.

Setting holb = 1 activates circuitry that attempts to prevent a backlogged conversation stalling other port traffic by using up all the memory buffers. Because the number of buffers charged to a particular port is always compared with the number of buffers left, there is no threshold register for this mode.

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Contents Description MII MAC MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interface100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail Port no Head Statistic Tail 0x90ExDMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management framesState of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portVlan ID FCSTpid TCI CRCTNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processingMAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control OutcomeM08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name FunctionDirected Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXDM08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Compatibility with future device revisions Port LED StatesCollision LED States State DisplayPCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayBUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDJtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist StatusIale Frame routingVlan support Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portPort trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitTiming requirements over recommended operating conditions Jtag interface Control signalsReset see Figure Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii transmit see Figure Gmii portGmii receive see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureRdram interface Rdram see FigureDtxclk Drxclk Dbusctrl DbusenSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice
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