Texas Instruments TNETX4090 Directed Format Receive Pretag Bit Definitions, Ring-cascade topology

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

			Table 12. Directed Format Receive Pretag Bit Definitions

	BIT	NAME	FUNCTION

			One. Indicates directed format. The frame is routed to port(s) specified in portvector that are enabled (disabled in
			portxcontrol = 0), regardless of whether the destination address is unicast or multicast (i.e., the destination address
			is not examined).
	31	1	The internal frame-routing algorithm is bypassed and has no effect on frame routing. The TxBlockPorts,
			RxUniBlockPorts, and RxMultiBlockPorts registers also have no effect on frame reception or transmission.
			Portvector is not examined to see if the source port has been specified as a destination port, so it is possible to send
			a frame back out of port 8. If portvector is 0, the frame is discarded.

	30±10	reserved	Reserved. Bits 30±10 are ignored.

	9±0	portvector	Destination port vector. A bit for each port on this device. A 1 in position n indicates the frame is destined for port n
	9±0	portvector	on this device.
			on this device.

ring-cascade topology

The ringports register allows port 8 to be used to cascade multiple TNETX4090 devices using a full-duplex ring-cascade topology (see Figure 7).



	RXD				FLOW		COL			TXD
					Port 8

			TNETX4090
0 1			2		3		4 5			6		7



	RXD				FLOW		COL			TXD
					Port 8

			TNETX4090
0 1			2		3		4 5			6		7

	RXD				FLOW		COL			TXD
					Port 8

			TNETX4090
0 1			2		3		4 5			6		7

Figure 7. Ring-Cascade Topology

This configuration provides a way to construct a higher port-density system using three or more TNETX4090s.

Setting the portvector bit corresponding to this port in RingPorts modifies the normal behavior of the switch in several ways to enable the ring topology.

DFrames received on this port can be retransmitted out through the same port. This allows frames destined for a nonring port on another switch in the ring to pass through this switch.

DFrames transmitted from a ring port have an out-of-band pretag in the clock cycle before Mxx_TXEN is asserted. The contents of the pretag are determined as follows:

±If the transmitted frame was received on a nonring port, the pretag consists of the ringid field from RingPorts, replicated on Mxx_RXD3±Mxx_RXD0 and Mxx_RXD7±Mxx_RXD4.

±If the transmitted frame was received on a ring port, the pretag is the same as the received pretag.

40	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents Description MII MAC MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExDMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management framesState of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portVlan ID FCSTpid TCI CRCTNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processingMAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name FunctionDirected Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Compatibility with future device revisions Port LED StatesCollision LED States State DisplayPCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayBUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDJtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist StatusVlan support Frame routingIale Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portPort trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureRdram interface Rdram see FigureDtxclk Drxclk Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice