Texas Instruments TNETX4090 specifications Interaction of Eeprom load with the SIO register

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

EEPROM interface (continued)

After the initial start condition, a slave address containing a device address of 000 is output on EDIO, and then EDIO is observed for an acknowledge from the EEPROM. If an acknowledge is received, operation continues for the 24C02 EEPROM. If none is received, a stop condition is generated, followed by another start condition and slave address, this time containing a device address of 101. If this receives no acknowledge, no EEPROM is present, and device operation continues, using the current register settings (i.e., those following a hardware reset, or those previously entered by software).

When this device is driving EDIO, it drives out only a strong logical 0. When a logical 1 is intended to be driven out, the terminal must be resistively pulled high. An on-chip 50-∝A current-source pullup device is provided on this terminal. The system designer must decide if this is sufficient to achieve a logical 1 level in a timely manner or if an external supplementary resistor is required.

Multiple bus masters are not supported on the EEPROM interface because the ECLK terminal always is driven by the device with a strong 0/strong 1 (i.e., not a strong 1/resistively pulled-up 1).

An Ethernet CRC check is used to ensure the EEPROM data is valid. The 4-byte CRC should be placed within the EEPROM in four data bytes immediately following the last byte to be loaded (equivalent to locations 0x00FC±0x00FF, just above SysControl). As each byte is loaded from the EEPROM, the bits within that byte are entered into the CRC checker bit-wise, most significant bit first.

A valid CRC always must be provided by the EEPROM. The EEPROM data for the most significant bit of SysControl is withheld until the CRC computed by the device has been checked against the one read from the EEPROM. If the CRC is invalid:

DThe reset bit is set to 1 in SysControl, load and initd are both 0, and the TNETX4090 does not begin operation.

DThe fault LED is illuminated and remains in that state until the TNETX4090 is hardware reset or until load in SysControl is set to 1.

interaction of EEPROM load with the SIO register

The EDIO terminal is shared with the SIO register edata bit. The edata and etxen bits must not both be set to 1 when the load bit is set or the EDIO terminal is held at resistive 1 and the EEPROM load fails.

The value of the eclk bit in SIO is don't care when load is set, but to ensure the EEPROM does not see a glitch on its clock signal, the load bit should not be set until the minimum clock high or low time required by the EEPROM on its clock signal has expired since the eclk bit was last changed.

The SIO register is not loaded during the EEPROM download.

summary of EEPROM load outcomes

Table 14 summarizes the various states of register bits and the fault LED for each possible outcome following an EEPROM load attempt.

Table 14. Summary of EEPROM Load Outcomes

OUTCOME

STOP

LOAD

INITD²

FAULT LED

ECLK

Successful load

0

0

1

0³

Not locked

No EEPROM present

0

0

0

0³

Locked

CRC error detected

1

0

0

1

Not locked

 

 

 

 

 

 

² Assuming the start bit was set to 1 by the EEPROM load

³Assuming the fault bit in LEDControl = 0 and no memory system parity error is detected

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Contents Description DMA MIIMAC MII MAC Eeprom CPU I/FPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interfaceM08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailReceiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup StatisticsIeee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware ResetCRC Vlan IDFCS Tpid TCITNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priorityMAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement BackoffSpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow controlPretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit DefinitionsTNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes State Display Compatibility with future device revisionsPort LED States Collision LED StatesMulti-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp testSout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDDJtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instructionVlan support Frame routingIale Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmissionAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingExtended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports RegisterFlow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limitInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureDbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk DrxclkDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice
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