Texas Instruments TNETX4090 specifications 10-/100-Mbit/s MII ports 0±7

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

10-/100-Mbit/s MII (ports 0±7)

speed, duplex, and flow-control negotiation

Each individual port can operate at 10 Mbit/s or 100 Mbit/s in half or full duplex, and can indicate (or not) support of IEEE Std 802.3 flow control. The operating modes for each port can be negotiated between the MACs and the PHYs after power up, by setting neg in PortxControl. This provides for unmanaged operation, when using PHYs that support this signaling scheme.

If neg = 1, negotiation is initiated via the Mxx_LINK signal being driven low by the PHY. As long as Mxx_LINK is low, the MAC indicates the capabilities it wishes the PHY to negotiate with. It outputs on:

DMxx_TXD0 is the desired duplex (0 = half, 1 = full). This signal reflects reqhd in the appropriate PortxControl register.

DMxx_TXD1 is the desired IEEE Std 802.3 flow-control mode (0 = no pause, 1 = pause required). This signal reflects the inverse of the value of reqnp in the appropriate PortxControl register.

DMxx_TXD2 is the desired speed (0 = 10 Mbit/s, 1 = 100 Mbit/s required). This signal reflects the inverse of the value of req10 in the appropriate PortxControl register.

Mxx_TD3 does not take part in the negotiation process and outputs as 0 while Mxx_LINK is low.

As long as Mxx_LINK is low, the PHY outputs on:

DMxx_RXD0 is the result of duplex negotiation (0 = half, 1 = full) that is recorded in the duplex bit of the appropriate PortxStatus register.

DMxx_RXD1 is the result of flow-control negotiation (0 = no pause, 1 = pause supported) that is recorded in the pause bit of the appropriate PortxStatus register.

DMxx_RXD2 is the result of speed negotiation (0 = 10 Mbit/s, 1 = 100 Mbit/s supported) that is recorded in the speed bit of the appropriate PortxStatus register.

Mxx_RXD3 is ignored by the switch when link is low.

If the switch is autobooted via an EEPROM, this negotiation is automatic (if the neg bit of the appropriate PortxControl register is set to 1 by the EEPROM load). The switch is active and outputs valid requests on Mxx_TXD0, Mxx_TXD1, and Mxx_TXD2 before Mxx_LINK is taken high by the PHY (see Figure 3).

If, however, a switch requires software initiation, or at a later time, software desires a change in the mode of a port, it must request the PHY to drive Mxx_LINK low to begin renegotiation. This is achieved by writing to the control registers within the PHY via the serial MII interface.

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Contents Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice
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