Texas Instruments TNETX4090 specifications ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET

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							TNETX4090
		ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET						SWITCH
					SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

		Table 2. DIO Internal Register Address Map (Continued)

BYTE 3		BYTE 2		BYTE 1		BYTE 0		DIO
BYTE 3		BYTE 2		BYTE 1		BYTE 0	ADDRESS
							ADDRESS

	SysControl				StatControl			0x00F8

		Reserved (for EEPROM CRC)					0x00FC

			VLAN0Ports					0x0100

			VLAN1Ports					0x0104

			VLAN2Ports					0x0108

			VLAN3Ports				0x010C

			VLAN4Ports					0x0110

			VLAN5Ports					0x0114

			VLAN6Ports					0x0118

			VLAN7Ports				0x011C

			VLAN8Ports					0x0120

			VLAN9Ports					0x0124

			VLAN10Ports					0x0128

			VLAN11Ports				0x012C

			VLAN12Ports					0x0130

			VLAN13Ports					0x0134

			VLAN14Ports					0x0138

			VLAN15Ports				0x013C

			VLAN16Ports					0x0140

			VLAN17Ports					0x0144

			VLAN18Ports					0x0148

			VLAN19Ports				0x014C

			VLAN20Ports					0x0150

			VLAN21Ports					0x0154

			VLAN22Ports					0x0158

			VLAN23Ports				0x015C

			VLAN24Ports					0x0160

			VLAN25Ports					0x0164

			VLAN26Ports					0x0168

			VLAN27Ports				0x016C

			VLAN28Ports					0x0170

			VLAN29Ports					0x0174

			VLAN30Ports					0x0178

			VLAN31Ports				0x017C

			VLAN32Ports					0x0180

			VLAN33Ports					0x0184

			VLAN34Ports					0x0188

			VLAN35Ports				0x018C

			VLAN36Ports					0x0190

			VLAN37Ports					0x0194

			VLAN38Ports					0x0198

			VLAN39Ports				0x019C

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents Description DMA MIIMAC MII MAC Eeprom CPU I/FPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interfaceM08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailReceiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup StatisticsIeee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware ResetCRC Vlan IDFCS Tpid TCITNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priorityMAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement BackoffSpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow controlPretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit DefinitionsTNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes State Display Compatibility with future device revisionsPort LED States Collision LED StatesMulti-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp testSout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDDJtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instructionVlan support Frame routingIale Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmissionAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingExtended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports RegisterFlow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limitInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureDbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk DrxclkDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice